Measurement Computing PCI-DAS6023 - Manual (Page 18)

18
Chapter 3
Functional Details
Basic architecture
Figure 4 shows a simplified block diagram of the PCI-DAS6023 and PCI-DAS6025. The PCI-DAS6025
provides all of the functional elements shown in the diagram. The PCI-DAS6023 does not provide D/A outputs,
and has eight bits of TTL digital I/O rather than the 32 digital inputs/outputs provided by the PCI-DAS6025.
The two boards are identical in all other respects.
The STC (System Timing and Control) is the logical center for all DAQ, DIO, and DAC (if applicable)
operations. It communicates over two major busses, a local bus and a memory bus.
The local bus carries digital I/O data and software commands from the PCI Bus Master. Two Direct Memory
Access (DMA) channels provide data transfers to the PC.
Primarily, the memory bus carries A/D and D/A (PCI-DAS6025 only) related data and commands. There are
three buffer memories provided on the memory bus:

The Queue Buffer is an 8K configuration memory. It can be used for storing programmed channel
numbers, gains, and offsets.
 The ADC Buffer is an 8K FIFO (First In, First Out) for temporary storage of scanned and converted analog
inputs.
 The DAC 16K Buffer can be used for storing data to be output as analog waveforms. (This function only
applies to the PCI-DAS6025.)
Auxiliary input and output interface
The board’s 100-pin I/O connector provides six software-selectable inputs and three software-selectable
outputs. The signals are user-configurable clocks, triggers and gates.
Refer to " DAQ signal timing " on page 21 for additional information and timing requirements for the signals.
The "Auxiliary I/O signals" table on page 19 defines the possible and default signals that can be used on the
nine pins.
D/A signals
The D/A signals are applicable to the PCI-DAS6025 only.