Measurement Computing CIO-DAS16/M1 - Manual (Page 28)

24
5. SPECIFICATIONS
Power consumption
+5V 1.8A typ, 2.7 A max
-5V 55mA typ, 70mA max
+12V 70mA typ, 91mA max
-12V 60mA typ, 82mA max
Analog input section
A/D converter type AD1671J
Resolution 12 bits
Number of channels 8 differential
Input ranges ±10V, ±5V, ±2.5V, ±1.25V,±.625V, 0 to 10V, 0 to 5V, 0 to
2.5V, 0 to 1.25V fully programmable
Polarity Unipolar/Bipolar, software selectable
A/D pacing Programmable: internal counter, external source (Din0,
rising edge) or software polled
Data transfer Word wide from 1024 sample FIFO via REP INSW,
interrupt, DT Connect or software polled
Polarity Unipolar/Bipolar software selectable
A/D Trigger sources External polled gate trigger (DIn0, active high),
A/D Triggering Modes
Digital:
Gated pacer, software polled. Gate disabled after trigger
A/D conversion time 0.8 µs
Throughput 1 MHz max through DT connect to external memory,
700kHz typical to PC memory (system-dependent)
Relative Accuracy 0.01% of reading, ±1bit (source impedance < 1ohm)
Differential NonLinearity 11 bits
Integral Linearity error ±2.5 LSBs max
Offset Error Trimmable to 0 by potentionmeter
Common Mode Range ±10V
CMRR (60Hz, Vin = CMR) 72dB min
No missing codes guaranteed 11 bits
Gain drift (A/D specs) ±30ppm/°C
Input leakage current (@25 Deg C) < 200nA
Input impedance Min 10Meg Ohms
Absolute maximum input voltage ±15V
DT Connect
Mode Master only
Transfer rate 1 Mega Word / second
Enable Programmable
Misc Compatible with Mega-FIFO