Measurement Computing CIO-DAS16/M1 User Manual
Page 19
15
IRQDATA is set according to the condition of the S1 and S0 bits of BASE + 5 register. This bit is set to 1
when:
S1 S0
0 0
Single A/D conversion is done.
0 1
Not applicable.
1 X
Total counter = 0 (meaning the total counter has reached terminal count), OR, the FIFO
reaches half full (512)
TRGSTAT: Pre-trigger status. Reads 1 if trigger has occurred. Pre-trigger must have been enabled.
OVRUN:
Over-run status bit. Is set to 1 at the A/D conversion that occurs after:
A DT-Connect handshake fails, or
The FIFO buffer is full.
This bit is cleared (set to 0) by either DTEN = 0 or by clearing the FIFO (write 0 to
BASE + 6). Stop the pacer before clearing the overrun bit.
TOOFAST: When set, the FIFO buffer is cleared automatically when half-full.
If this bit is set to 1, the DT-Connect must be in use or many conversions may be lost. The interrupt on
FIFO half-full will still function when this bit is set so that interrupt must be handled correctly. Set this bit
and use DT-Connect whenever the A/D conversion rate desired exceeds the REP-INSW rate of the target
computer.
PRETRIG: When set to 1, enables pre-trigger mode. TRIG0 must be set to 1 also.
When set to 0, disables pre-trigger mode.
DTEN:
When set to 1, enables DT-Connect data transfers. Disables at 0.
CTR0:
Selects source of CTR0 clock input. If set to 1, source is on-board
XTAL:
Gated
by
pin
21
of
the
37-pin
connector.
If set to 0, the source is the clock signal you supply to pin 21.
TRIG0:
When set to 1, enables pin 25 as the external trigger (trigger signal must be active high).
When set to 0, the external trigger is disabled. The trigger is a low to high transition which initiates a
block of A/D samples. The external trigger can be used only with the on-board XTAL pacer signal. If the
A/D is externally paced, it is not possible to use an external trigger.
4.6.3
Four-Bit Digital I/O Reg isters
BASE ADDRESS + 3
When read:
7
6
5
4
3
2
1
0
0
0
0
0
DIN 3
DIN
2,also
CTR0 Gate
DIN 1
DIN 0,also
TRIGIN