Measurement Computing CIO-DAS16/M1 - Manual (Page 14)

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4. REGISTER ARCHITECTURE
4.1 DATA TRANSFERS
The CIO-DAS16/M1 bus interface is a PC/AT bus interface. A/D data can be transferred via REP-INSW
(high speed block transfers), Interrupt Service Routine or software polled. Digital and counter data can be
transferred via interrupt or it can be software-polled.
Data may also be transferred directly to a memory card (such as the MEGA-FIFO) through the DT-
Connect port. This method allows the highest transfer speeds and lowest PC overhead.
4.2 FIFO DATA BUFFER
The First In First Out (FIFO) buffer is a specialized memory 1024 samples deep. After each conversion,
the A/D data is transferred to the FIFO memory. Samples are retrieved from the FIFO by the computer
program which stores the data in the PC's memory. This can be a language or an application program.
The FIFO is active all the time, regardless of A/D transfer mode.
4.3 CHANNEL/GAIN QUEUE
The channel/gain queue is implemented with a simple 8-bit up-counter, a 256-byte memory and some
control logic. Each channel/gain (C/G) pair is loaded as one byte.
IMPORTANT NOTE: Any individual channel can be sampled so long as it is the only sample in the
channel/gain list. For example, sampling channel 3 repeatedly at 1 MHz is allowed. However, when more
than one channel is in the channel gain list, adhere to the following rules:
1) There must be an even number of entries in the queue.
2) Even channels must be at even queue addresses (0, 2, 4, ...)
3) Odd channels must be at odd queue addresses (1, 3, 5, ...)
Failure to follow queue-sequencing rules will result in scrambling of data between channels.
The first C/G in the scan is loaded into C/G memory address 0. The second C/G in the scan is loaded into
C/G memory address 1, and so on until the last C/G in the scan is the last item loaded into C/G memory.
A register stores the most recently written C/G memory address and this C/G element becomes the
RESTART ADDRESS. Each time the restart address is reached, the C/G address pointer will be reset to
point to address 0, which contains the first element in the C/G list.
When the A/D starts the acquisition scan, the first sample is controlled from the first entry in the C/G
memory, address 0. The second sample is controlled by the second entry made in C/G memory and so on
until the RESTART ADDRESS (last entry) address of C/G memory is reached. At this point the C/G
memory pointer is reset to the address 0 and the sequence of C/G begins again. The process will repeat as
long as the A/D is acquiring data.