beautypg.com

Chapter 7, Boot – DFI DT122-HR Manual User Manual

Page 49

background image

www.dfi .com

49

Chapter 7 BIOS Setup

Chapter 7

Setup Prompt Timeout

Selects the number of seconds to wait for the setup activation key. 65535(0xFFFF) denotes

indefinite waiting.

Bootup NumLock State

This allows you to determine the default state of the numeric keypad. By default, the sys-

tem boots up with NumLock on wherein the function of the numeric keypad is the number

keys. When set to Off, the function of the numeric keypad is the arrow keys.

Quiet Boot

Enables or disables the quiet boot function.

Boot

Number of seconds to
wait for setup activation
key.
65535(0xFFFF) means
indefi nite waiting.

Aptio Setup Utility - Copyright (C) 2011 American Megatrends, Inc.

Version 2.14.1219. Copyright (C) 2011 American Megatrends, Inc.

Boot Confi guration

Setup Prompt Timeout

Bootup NumLock State

Quiet Boot

CSM16 Module Version

Boot Option Priorities

Save & Exit

Chipset

Advanced

Security

Main

Boot



Select Screen



Select Item

Enter: Select
+/-: Change Opt.
F1: General Help
F2: Previous

Values

F3: Optimized

Defaults

F4: Save & Exit
ESC: Exit

5

[On]

[Disabled]

07.63

USB Configuration

Control the USB EHCI
(USB 2.0) functions.
One EHCI controller must
always be enabled.

Aptio Setup Utility - Copyright (C) 2011 American Megatrends, Inc.

Version 2.14.1219. Copyright (C) 2011 American Megatrends, Inc.

USB Confi guration

EHCI1

EHCI2

[Enabled]

[Enabled]

Chipset



Select Screen



Select Item

Enter: Select
+/-: Change Opt.
F1: General Help
F2: Previous

Values

F3: Optimized

Defaults

F4: Save & Exit
ESC: Exit

EHCI1 and EHCI2

These fields are used to enable or disable USB 2.0.

PCI Express Configuration

Enable or disable PCI
Express Clock Gating for
each root port.

Aptio Setup Utility - Copyright (C) 2011 American Megatrends, Inc.

Version 2.14.1219. Copyright (C) 2011 American Megatrends, Inc.

PCI Express Confi guration


PCI Express Clock Gating

PCIE Port 1 is assigned to LAN



PCI Express Root Port 1



PCI Express Root Port 2



PCI Express Root Port 3

[Enabled]

Chipset



Select Screen



Select Item

Enter: Select
+/-: Change Opt.
F1: General Help
F2: Previous

Values

F3: Optimized

Defaults

ESC: Exit

PCI Express Clock Gating

Enables or disables PCI Express Clock Gating for each root port.

PCI Express Root Port 1 to PCI Express Root Port 3

Controls the PCI Express Root Port.