Comtech EF Data DMDVR20 LBST Rev 1.1 - Manual (Page 23)

Theory of Operation DMDVR20 LBST Satellite Modem
3-2 TM136 – Rev. 1.1
In the complex downconverter, the signal for demodulation is amplified and sent through a
variable wideband attenuator for AGC. The gain-controlled signal is then passed through a
complex downconverter to a low IF.
Figure 3-2. IF Card Block Diagram
3.0.2 Baseband Processing Printed Circuit Card
The advent of million-plus gate count FPGAs, advanced logic synthesis tools, and DSPs
providing hundreds of MIPs enabled the design of a software configurable modem. Large, fast
FPGAs now provide designers with what is essentially an on the fly programmable ASIC. High
speed, complex digital logic functions that previously could only be implemented in dedicated
integrated circuits are now downloaded from a micro-controller through a serial or peripheral
interface. When a new digital logic function is needed, a new configuration file is loaded into the
FPGA. There is no limit to the number of digital logic configurations available to the FPGA, aside
from the amount of Flash memory available to the system microprocessor for storage of
configuration files.
The Baseband Processing Printed Circuit Card provides a flexible architecture that allows
different modes of terrestrial and satellite framing, various FEC options, and several different
modulation/demodulation formats. Also included on the Baseband Printed Circuit Card are three
synchronous interfaces, an EIA-530 Interface supporting RS-422, V.35, and RS-232. All three
interfaces are provided on the same DB-25 Connector, and are selectable from the front panel.