Table 4-8, Table 4-9, Mechanical and connector information – Artesyn RTM-ATCA-736x-DD Installation and Use (June 2014) User Manual
Page 54
Mechanical and Connector Information
RTM-ATCA-736X-DD Installation and Use (6806800L82C)
54
Table 4-8 Connector J32, Miscellaneous RTM Signal Descriptions
Row
Interface
A
B
C
D
E
F
G
H
1
PCIe-9
3
P9_Rx0+
P9_Rx0-
P9_Tx0+
P9_Tx0-
P9_Rx1+
P9_Rx1-
P9_Tx1+
P9_Tx1-
2
PCIe-9
3
P9_Rx2+
P9_Rx2-
P9_Tx2+
P9_Tx2-
P9_Rx3+
P9_Rx3-
P9_Tx3+
P9_Tx3-
3
PCIe-8
2
P8_Rx0+
P8_Rx0-
P8_Tx0+
P8_Tx0-
P8_Rx1+
P8_Rx1-
P8_Tx1+
P8_Tx1-
4
PCIe-8
2
P8_Rx2+
P8_Rx2-
P8_Tx2+
P8_Tx2-
P8_Rx3+
P8_Rx3-
P8_Tx3+
P8_Tx3-
5
PCIe-7
2
P7_Rx0+
P7_Rx0-
P7_Tx0+
P7_Tx0-
P7_Rx1+
P7_Rx1-
P7_Tx1+
P7_Tx1-
6
PCIe-7
2
P7_Rx2+
P7_Rx2-
P7_Tx2+
P7_Tx2-
P7_Rx3+
P7_Rx3-
P7_Tx3+
P7_Tx3-
7
PCIe-6
P6_Rx0+
P6_Rx0-
P6_Tx0+
P6_Tx0-
P6_Rx1+
P6_Rx1-
P6_Tx1+
P6_Tx1-
8
PCIe-6
P6_Rx2+
P6_Rx2-
P6_Tx2+
P6_Tx2-
P6_Rx3+
P6_Rx3-
P6_Tx3+
P6_Tx3-
9
PCIe
P9_Clk10
0+
P9_Clk1
00-
P8_Clk10
0+
P8_Clk1
00-
P7_Clk1
00+
P7_Clk1
00-
P6_Clk100
+
P6_Clk1
00-
10
POWER
VP12
n.c.
n.c.
VP12
n.c.
88
_PS0_N
88_ DI
88_ D0
1
PCIe ports 8 and 7 may be combined to function as single x8 PCI-express port through BIOS settings. Port 8 become
bits 4-7.
2
PCIe ports 10 and 9 may be combined to function as single x8 PCI-express port through BIOS settings. Port 10
become bits 4-7.
3
PCIe ports 10,9,8,7 may be combined to function as single x16 PCI-express port through BIOS settings. Port 10
becomes bits 15-12.
Table 4-9 Connector J32, Miscellaneous RTM Signal Descriptions
Connector
Description
P9_Rx, P9_Tx, P9_Clk100+
(Unused) Port #9 PCI express differential signal pairs for transmit and receive; and
100MHz reference clock
P8_Rx, P8_Tx, P8_Clk100+
Route to LSI 1064E Port #8 PCI express differential signal pairs for transmit and
receive; and 100 MHz reference clock
P7_Rx, P7_Tx, P7_Clk100+
Route to LSI 1064E. Port #7 PCI express differential signal pairs for transmit and
receive; and 100 MHz reference clock
P6_Rx, P6_Tx, P6_Clk100+
Route to Intel 82580. Port #6 PCI express differential signal pairs for transmit
receive and 100 MHz reference clock