Altera Stratix IV GT 100G - Manual (Page 39)

Chapter 6: Board Test System 6–17
Using the Board Test System
October 2010 Altera Corporation Stratix IV GT 100G Development Kit User Guide
The CFP Tab
The CFP tab allows you to do loopback testing on this interface using different data
patterns, PMA settings, and clock speeds using the Clock Control application.
Figure 6–9 shows the CFP tab.
1
You must have the CFP loopback board installed on your 100G development board
for this test to work correctly.
The CFP loopback board can be plugged into the connector in either direction. On
SIDE A, the transceiver channels go through a retimer device and loops these
channels back internally to the FPGA. On SIDE B, the transceiver channels go directly
from the receiver to the transmitter without any help from the retimer device. For
both sides you need to connect the two SMA connectors with SMA cables. For
example, for SIDE A, connect a SMA cable between J6 and J7 and between J9 and J10.
For SIDE B, connect a SMA cable between J1 and J5 and J2 and J6.
Figure 6–9. The CFP Tab