The ssram tab, The ssram tab –11, Read –11 – Altera Stratix IV GT 100G User Manual
Page 33: Read

Chapter 6: Board Test System
6–11
Using the Board Test System
October 2010
Altera Corporation
Stratix IV GT 100G Development Kit User Guide
The SSRAM Tab
The SSRAM tab allows you to read and write SRAM and flash memory on your
board.
Figure 6–6
shows the SSRAM tab.
The following sections describe the controls on the SSRAM tab.
Read
The Read control reads the SSRAM on your board. To see the SSRAM contents, type a
starting address in the text box and click Read. Values starting at the specified address
appear in the table. The SSRAM addresses display in the format the Nios II processor
within the FPGA uses, that is, each SSRAM address is offset by 0x00200000. Thus, the
first location in SSRAM appears as 0x00200000 in the GUI.
1
If you enter an address outside of the 0x00200000 to 0x003FFFFF SSRAM address
space, a warning message identifies the valid SSRAM address range.
Figure 6–6. The SSRAM Tab
- MAX 10 JTAG (15 pages)
- MAX 10 Power (21 pages)
- Unique Chip ID (12 pages)
- Remote Update IP Core (43 pages)
- Device-Specific Power Delivery Network (28 pages)
- Device-Specific Power Delivery Network (32 pages)
- Hybrid Memory Cube Controller (69 pages)
- ALTDQ_DQS IP (117 pages)
- MAX 10 Embedded Memory (71 pages)
- MAX 10 Embedded Multipliers (37 pages)
- MAX 10 Clocking and PLL (86 pages)
- MAX 10 FPGA (26 pages)
- MAX 10 FPGA (56 pages)
- USB-Blaster II (22 pages)
- GPIO (22 pages)
- LVDS SERDES (27 pages)
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- ALTDQ_DQS2 (100 pages)
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- Cyclone V Avalon-MM (166 pages)
- Cyclone III FPGA Starter Kit (36 pages)
- Cyclone V Avalon-ST (248 pages)
- Stratix V Avalon-ST (286 pages)
- Stratix V Avalon-ST (293 pages)
- DDR3 SDRAM High-Performance Controller and ALTMEMPHY IP (10 pages)
- Arria 10 Avalon-ST (275 pages)
- Avalon Verification IP Suite (224 pages)
- Avalon Verification IP Suite (178 pages)
- FFT MegaCore Function (50 pages)
- DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP (140 pages)
- Floating-Point (157 pages)
- Integer Arithmetic IP (157 pages)
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- JESD204B IP (158 pages)
- Low Latency Ethernet 10G MAC (109 pages)
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- Nios II Embedded Evaluation Kit Cyclone III Edition (3 pages)
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- Parallel Flash Loader IP (57 pages)
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- RAM-Based Shift Register (26 pages)
- RAM Initializer (36 pages)
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