Altera MAX II User Manual
Page 27
Altera Corporation
Development Kit Version 1.1.0
2–19
July 2005
MAX II Development Kit Getting Started User Guide
Getting Started
Figure 2–7. Device Manager Window
5.
If successful communication is established, the LCD displays
Connected to PC!
.
6.
The PC Application allows you to read from and write to most of
the components on the MAX II board. Note the Default Encoding
drop down box in the Control Options section of the user interface.
This controls how the MAX II device interprets the data sent to and
received from the MAX II board. If you select Hexadecimal, the PC
will treat all data as hexadecimal characters. If you select ASCII,
then the PC will interpret all data as ASCII.
1
This demo relies on the appropriate transmission of data
from the PC to the board. If corrupt data is transmitted,
errors will occur. The application on the PC may be
unaware of hardware errors. The board will show hardware
errors by flashing the LEDs. If you see that the LEDs are
flashing, click the Close Port button on the PC application
and press S1 on the development board. You can then
re-open the port and use the demo as normal.
- MAX 10 JTAG (15 pages)
- MAX 10 Power (21 pages)
- Unique Chip ID (12 pages)
- Remote Update IP Core (43 pages)
- Device-Specific Power Delivery Network (28 pages)
- Device-Specific Power Delivery Network (32 pages)
- Hybrid Memory Cube Controller (69 pages)
- ALTDQ_DQS IP (117 pages)
- MAX 10 Embedded Memory (71 pages)
- MAX 10 Embedded Multipliers (37 pages)
- MAX 10 Clocking and PLL (86 pages)
- MAX 10 FPGA (26 pages)
- MAX 10 FPGA (56 pages)
- USB-Blaster II (22 pages)
- GPIO (22 pages)
- LVDS SERDES (27 pages)
- User Flash Memory (33 pages)
- ALTDQ_DQS2 (100 pages)
- Avalon Tri-State Conduit Components (18 pages)
- Cyclone V Avalon-MM (166 pages)
- Cyclone III FPGA Starter Kit (36 pages)
- Cyclone V Avalon-ST (248 pages)
- Stratix V Avalon-ST (286 pages)
- Stratix V Avalon-ST (293 pages)
- DDR3 SDRAM High-Performance Controller and ALTMEMPHY IP (10 pages)
- Arria 10 Avalon-ST (275 pages)
- Avalon Verification IP Suite (224 pages)
- Avalon Verification IP Suite (178 pages)
- FFT MegaCore Function (50 pages)
- DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP (140 pages)
- Floating-Point (157 pages)
- Integer Arithmetic IP (157 pages)
- Embedded Peripherals IP (336 pages)
- JESD204B IP (158 pages)
- Low Latency Ethernet 10G MAC (109 pages)
- LVDS SERDES Transmitter / Receiver (72 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (3 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (80 pages)
- IP Compiler for PCI Express (372 pages)
- Parallel Flash Loader IP (57 pages)
- Nios II C2H Compiler (138 pages)
- RAM-Based Shift Register (26 pages)
- RAM Initializer (36 pages)
- Phase-Locked Loop Reconfiguration IP Core (51 pages)
- DCFIFO (28 pages)