Altera MAX II - Manual (Page 19)

Altera Corporation Development Kit Version 1.1.0 2–11
July 2005 MAX II Development Kit Getting Started User Guide
Getting Started
V_INT shows the Core V
CC
rise time, and the rise time variation caused
by POT1. ACTIVE_IO is driven by a MAX II user I/O pin that helps
demonstrate the instant MAX II becomes functional (powered-up and
configured).
Figure 2–4 shows a typical digital oscilloscope output. For this test the
V
CCINT
rise time is 10 ms. The device is functional at 2.18 V, well below the
minimum V
CC
level of 3.0 V. The I/O Pin starts out low, and at about a
core V
CC
of 1.25 V the I/O pull-up becomes active and the I/O goes to the
V
CCIO
level.
1
In the development board setup, the V
CCIO
ring is on a different
supply than V
CCINT
. The V
CCIO
ring is a constant 3.3 V and does
not power cycle when S5 is pressed.
In Figure 2–4 , the MAX II representative I/O (labeled Active I/O on the
test point on the board), switches to 0 V when V
CCINT
is at 2.18 V. It
switches after configuration is complete and the core registers are reset,
and released and the I/O are released. Once working, this I/O pin will
begin to oscillate with a high and low period equal to T
CONFIG
, the time
needed to move the configuration data from the Configuration Flash
Memory (CFM) to the configuration SRAM. The first falling edge on this
I/O (shown in the lighter color in
Figure 2–4 ) is when configuration is
complete. Measuring back the T
CONFIG
of the first low pulse width of this
Active I/O will show at approximately what core voltage configuration
started.