Altera Cyclone V GX FPGA - Manual (Page 29)

Chapter 6: Board Test System 6–13
The Clock Control
October 2012 Altera Corporation Cyclone V GX FPGA Development Kit
User Guide
Figure 6–7 shows the Clock Control U25 tab.
The following sections describe the Clock Control controls.
Serial Port Registers
The Serial port registers control (X2 tab) shows the current values from the Si570
registers.
f For more information about the Si570 registers, refer to the Si570/Si571 data sheet
available on the Silicon Labs website (
www.silabs.com ).
fXTAL
The fXTAL control shows the calculated internal fixed-frequency crystal, based on the
serial port register values.
For more information about the f
XTAL
value and how it is calculated, refer to the
Si570/Si571 data sheet available on the Silicon Labs website ( www.silabs.com ).
Target Frequency
The Target frequency control allows you to specify the frequency of the clock. Legal
values are between 10 and 810 MHz with eight digits of precision to the right of the
decimal point. For example, 421.31259873 is possible within 100 parts per million
(ppm). The Target frequency control works in conjunction with the Set New
Frequency
control.
Figure 6–7. The Clock Control - X2 Tab