Altera Cyclone V GX FPGA - Manual (Page 11)

October 2012 Altera Corporation Cyclone V GX FPGA Development Kit
User Guide
4. Development Board Setup
The instructions in this chapter explain how to set up the Cyclone V GX FPGA
development board.
Setting Up the Board
To prepare and apply power to the board, perform these steps:
1. The FPGA development board ships with its board switches preconfigured to
support the design examples in the kit. If you suspect your board might not be
currently configured with the default settings, follow the instructions in
“Factory
Default Switch Settings” on page 4–2 to return the board to its factory settings
before proceeding.
2. The FPGA development board ships with design examples stored in the flash
memory device. Verify the DIP switch (SW3.3) is set to the factory off (1) position
to load the design stored in the factory portion of flash memory.
1
The FPGA development board can be powered by the PCIe host adapter or the laptop
power adapter. If you want to power the board by the PCIe host system, plug the
FPGA development card into a standard PCIe connector. Alternatively, to power the
FPGA development board using the laptop power adaptor, perform the following two
steps:
3. Connect the 65 W, 15 VDC @ 4.3 A power supply to the DC Power Jack (J9) on the
FPGA board and plug the cord into a power outlet.
c Use only the supplied power supply. Power regulation circuitry on the
board can be damaged by power supplies with greater voltage, and a
lower-rated power supply may not be able to provide enough power for the
board.
4. Set the POWER switch (SW1) to the on position. When power is supplied to the
board, blue LED (D23) illuminates indicating that the board has power.
The MAX V device on the board contains (among other things) a parallel flash loader
(PFL) megafunction. When the board powers up, the PFL reads a design from flash
memory and configures the FPGA. The DIP switch (SW3.3) controls which design to
load. When the switch is in the factory off (1) position, the PFL loads the design from
the factory portion of flash memory.
1
The kit includes a MAX V design which contains the MAX V PFL megafunction. The
design resides in the dir>\kits\cycloneVGX_5cgxfc7df31_fpga\examples\max5 directory.
When configuration is complete, the Config Done LED (D15) illuminates, signaling
that the Cyclone V GX device configured successfully.