Altera CIC MegaCore Function User Manual
Page 6

Device
Filter Type
ALM
Memory
Registers
f
MAX
(MHz)
M10K
M20K
Primary
Secondary
Arria V Interpolator 5
Channels 3
Interfaces
886
27
--
1,776
17
232.61
Arria V Interpolator
Convergent
Rounding
352
1
--
785
12
304
Arria V Interpolator
Variable Rate
Change
889
27
--
1,772
23
235
Cyclone
V
Decimator
492
2
--
1,137
17
182
Cyclone
V
Decimator 5
Channels
1,162
2
--
3,748
8
190.15
Cyclone
V
Decimator 5
Channels 3
Interfaces
906
37
--
1,719
9
204
Cyclone
V
Decimator
Hogenauer Pruning
352
1
--
784
14
246
Cyclone
V
Decimator
Truncation
463
2
--
1,054
4
177
Cyclone
V
Decimator Variable
Rate Change
917
37
--
1,730
5
193.27
Cyclone
V
Interpolator
324
1
--
709
37
264
Cyclone
V
Interpolator 5
Channels
760
1
--
2,383
11
235
Cyclone
V
Interpolator 5
Channels 3
Interfaces
890
27
--
1,747
48
168
Cyclone
V
Interpolator
Convergent
Rounding
352
1
--
784
14
246.06
Cyclone
V
Interpolator
Variable Rate
Change
894
27
--
1,725
70
165
Stratix
V
Decimator
515
--
1
1,152
6
377
Stratix
V
Decimator 5
Channels
1,176
--
1
3,750
8
413
1-4
CIC IP Core Performance and Resource Utilization
UG-CIC
2014.12.15
Altera Corporation
About The CIC IP Core
- MAX 10 JTAG (15 pages)
- MAX 10 Power (21 pages)
- Unique Chip ID (12 pages)
- Remote Update IP Core (43 pages)
- Device-Specific Power Delivery Network (28 pages)
- Device-Specific Power Delivery Network (32 pages)
- Hybrid Memory Cube Controller (69 pages)
- ALTDQ_DQS IP (117 pages)
- MAX 10 Embedded Memory (71 pages)
- MAX 10 Embedded Multipliers (37 pages)
- MAX 10 Clocking and PLL (86 pages)
- MAX 10 FPGA (26 pages)
- MAX 10 FPGA (56 pages)
- USB-Blaster II (22 pages)
- GPIO (22 pages)
- LVDS SERDES (27 pages)
- User Flash Memory (33 pages)
- ALTDQ_DQS2 (100 pages)
- Avalon Tri-State Conduit Components (18 pages)
- Cyclone V Avalon-MM (166 pages)
- Cyclone III FPGA Starter Kit (36 pages)
- Cyclone V Avalon-ST (248 pages)
- Stratix V Avalon-ST (286 pages)
- Stratix V Avalon-ST (293 pages)
- DDR3 SDRAM High-Performance Controller and ALTMEMPHY IP (10 pages)
- Arria 10 Avalon-ST (275 pages)
- Avalon Verification IP Suite (224 pages)
- Avalon Verification IP Suite (178 pages)
- FFT MegaCore Function (50 pages)
- DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP (140 pages)
- Floating-Point (157 pages)
- Integer Arithmetic IP (157 pages)
- Embedded Peripherals IP (336 pages)
- JESD204B IP (158 pages)
- Low Latency Ethernet 10G MAC (109 pages)
- LVDS SERDES Transmitter / Receiver (72 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (3 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (80 pages)
- IP Compiler for PCI Express (372 pages)
- Parallel Flash Loader IP (57 pages)
- Nios II C2H Compiler (138 pages)
- RAM-Based Shift Register (26 pages)
- RAM Initializer (36 pages)
- Phase-Locked Loop Reconfiguration IP Core (51 pages)
- DCFIFO (28 pages)