Altera Arria V GX - Manual (Page 27)

Chapter 6: Board Test System 6–5
Using the Board Test System
November 2014 Altera Corporation Arria V GX Starter Kit
User Guide
■ PSO —Sets the MAX V PSO register. The following options are available:
■ Use PSR —Allows the PSR to determine the page of flash memory to use for
FPGA reconfiguration.
■ Use PSS —Allows the PSS to determine the page of flash memory to use for
FPGA reconfiguration.
■ PSR —Sets the MAX V PSR register. The numerical values in the list corresponds
to the page of flash memory to load during FPGA reconfiguration. Refer to
Table 6–1 for more information.
■ PSS —Displays the MAX V PSS register value. Refer to Table 6–1 for the list of
available options.
1
Because the System Info tab requires that a specific design is running in the FPGA at
a specific clock speed, writing a 0 to SRST or changing the PSO value can cause the
Board Test System to stop running.
JTAG Chain
The JTAG chain control shows all the devices currently in the JTAG chain. The
Arria V GX device is always the first device in the chain. The JTAG chain is normally
mastered by the On-board USB-Blaster II.
f
If the JTAG chain cannot be detected using the On-Board USB-Blaster II, refer to the
initialization instructions on the
USB-Blaster Driver for Windows 7 and Windows
Vista web page or the USB-Blaster and USB-Blaster II Drivers for Windows XP web
page.
1 If you plug in an external USB-Blaster cable to the JTAG header (J9), the On-Board
USB-Blaster II is disabled.
1 DIP switch SW2 selects which interfaces are in the chain. Refer to Table 4–2 on
page 4–3 for detailed settings.
f
For details on the JTAG chain, refer to the Arria V GX Starter Board Reference Manual.
For USB-Blaster II configuration details, refer to the On-Board USB-Blaster II page.
Qsys Memory Map
The Qsys memory map control shows the memory map of the Qsys system on your
board.