Altera Device-Specific Power Delivery Network - Manual (Page 25)

1. Enter the ESR, ESL, and Lmnt values for the capacitors listed in the Custom field.
2. Enter the effective BGA via (loop) parasitics for the power supply being decoupled in the BGA Via &
Plane Cap field..
3. Enter the plane capacitance seen by the power/ground plane pair on the board for the power supply in
the BGA Via & Plane Cap field.
4. Enter the VRM parasitics, if available, in the Custom row of the VRM field.
5. Enter the effective spreading inductance seen by the decoupling capacitors in the Custom row of the
Spreading R and L field.
Deriving Decoupling in a Single-Rail Scenario
A power supply connects to only one power rail on the FPGA device in a single-rail scenario. The PDN
noise is created by the dynamic current change of the single rail. You determine Z
TARGET
and F
EFFECTIVE
based on the parameters related to the selected rail only.
The PDN tool 2.0 provides two ways to derive a decoupling network. You can set up the tool with the
information needed and let the tool derive the PDN decoupling for your system. You can also manually
enter the information and derive decoupling. To derive the desired capacitor combination:
1. Select the device/power rail to work with.
2. Select the parameter settings for the PDN components.
3. Enter the electric parameters to set Z
TARGET
and F
EFFECTIVE
.
You need to have a good estimate of the parameters entered to derive the proper decoupling guidelines
(Z
TARGET
and F
EFFECTIVE
). Although you need to determine those guidelines based on the worst-case
scenario, pessimistic settings result in hard-to-achieve guidelines and over design of your PCB
decoupling.
4. Derive the PCB decoupling scheme.
You must adjust the number and value of the PCB capacitors in the Decoupling Capacitor (Mid/High
Frequency) and Decoupling Capacitor (Bulk) fields to keep the plotted Z
EFF
below Z
TARGET
until
F
EFFECTIVE
. You can derive the decoupling for the selected power rail manually. You can also select the
Auto Decouple button and let the PDN tool 2.0 derive the decoupling scheme. If you are not able to
find a capacitor combination that meets your design goal, you can try to change the parameters at step
2 . For example, you can reduce the BGA via inductance used in the Calculate option by reducing the
BGA via length in the BGA_VIA tab and using the low option for plane spreading. These changes
reduce parasitic inductance and make it easier to achieve your decoupling goal. To achieve the low
spreading setting, you must place the mid to high frequency PCB capacitors close to the FPGA device.
You also must minimize the dielectric thickness between the power and ground plane. Refer to
Troubleshooting Z
EFF
if the Z
EFF
is too high or the number of capacitors for decoupling becomes too
high.
If you are not able to meet the Z
TARGET
requirement with the changes above, the PDN in your design may
have reached its physical limitation under the electrical parameters you entered for Z
TARGET
and
F
EFFECTIVE
. You should re-examine these parameters to check if they are overly pessimistic.
UG-01157
2015.03.06
Deriving Decoupling in a Single-Rail Scenario 25
Device-Specific Power Delivery Network (PDN) Tool 2.0 User Guide Altera Corporation
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