Echelon Neuron C - Manual (Page 166)

154 Additional Features
I/O Interrupts
The Series 5000 hardware supports two independent I/O interrupts, each derived
from one of the chip’s 12 I/O pins. Each of the two I/O interrupts can be
configured to trigger with any one of the following I/O signal conditions (but not a
combination of them):
• Rising edge of the I/O signal
• Falling edge of the I/O signal
• Both rising and falling edges of the I/O signal
• High level of the I/O signal
• Low level of the I/O signal
The interrupt source is independent of the I/O direction, that is, it works with
both input and output signals. In addition, both interrupts are independent of
each other. You can configure each I/O interrupt to trigger on separate I/O pins
or on the same I/O pin. If both trigger on the same pin, they could also trigger on
the same condition, although such a configuration is not likely to be useful to the
application. For example, both could trigger on the falling edge of IO_3. A more
useful example could have one I/O interrupt trigger with IO_3’s rising edge and
the other I/O interrupt trigger with IO_3’s falling edge, but note that you can also
declare a single I/O interrupt task that triggers with either edge of the I/O signal.
An interrupt that is configured to trigger on a high or low level of an I/O signal
continues to trigger as long as the level condition is met. For example, you could
trigger an interrupt to process a first-in first-out (FIFO) queue by specifying a
level signal to represent a non-empty queue, and the interrupt triggers
repeatedly until the level changes (when the queue is empty).
Timer/Counter Interrupts
As described in the I/O Model Reference , the Series 5000 chip hardware supports
two hardware timer/counters:
• Timer/counter 1 is connected to IO_0 (output) and IO_4..7 (input) through
a multiplexer
• Timer/counter 2 is dedicated to IO_1 (output) and IO_4 (input)
Both timer/counters can generate one optional timer/counter interrupt each. The
interrupt occurs when the counter overflows or underflows, or when the timer
event latch triggers, depending on which I/O model the timer/counter is defined
for.
For timer/counter I/O models that use multiplexed I/O pins, a timer/counter
interrupt task runs when any of the pins within the defined I/O model meet the
critera for an interrupt.
Periodic System Timer Interrupts
An application can also use the periodic system timer interrupt. The frequency
for this interrupt can be configured within a wide range (2.4 kHz to 625 kHz).
The periodic system timer cannot be stopped (it is always running), and its
frequency can be set only during compilation, but you can enable or disable the