S54 – cadence a max off time of ring, S55 – cadence b min on time of ring, S56 – cadence b max on time of ring – Maxim Integrated 73M2901CE AT Command User Manual
Page 35: 58 s57 – cadence b min off time of ring, S58 – cadence b max off time of ring, S59 – bit mapped register, S57 – cadence b min off time of ring
UG_2901CE_027
73M2901CE AT Command User Guide
Rev. 2.0
35
4.4.55
S54 – Cadence A Max Off Time of Ring
(Default = 120)
The value of this register sets the duration of the primary cadence maximum ring OFF time in units of
40ms.
4.4.56
S55 – Cadence B Min On Time of Ring
(Default = 0)
The value of this register sets the duration of the alternate cadence minimum ring ON time in units of
40ms.
4.4.57
S56 – Cadence B Max On Time of Ring
(Default = 0)
The value of this register sets the duration of the alternate cadence maximum ring ON time in units of
40ms.
4.4.58
S57 – Cadence B Min Off Time of Ring
(Default = 0)
The value of this register sets the duration of the alternate cadence minimum ring OFF time in units of
40ms.
4.4.59
S58 – Cadence B Max Off Time of Ring
(Default = 0)
The value of this register sets the duration of the alternate cadence maximum ring OFF time in units of
40ms.
4.4.60
S59 – Bit Mapped Register
(Default = 0)
Register S59 reflects the status of various options. This register is normally used as a read only register.
Register S59 is a bit mapped register whose bits are defined as follows:
Bit 0 In FSK: Skipped STOP, resync to it.
In QAM or PSK: Full equalizer back propagation.
Bit 1 16 way decisions in QAM receiver.
Bit 2 Scrambler invert flag ( whether inversion of next modulated bit should occur).
Bit 3 Scrambler history bit.
Bit 4 De-scrambler invert flag.
Bit 5 De-scrambler history bit.
Bit 6 Last received bit.
Bit 7 Last transmitted bit.