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2 visa-2 loopback test, Visa-2 loopback test, Figure 15: visa-2 loopback test flow chart – Maxim Integrated 73S12xxF Software User Manual

Page 91

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UG_12xxF_016

73S12xxF Software User Guide

Rev. 1.50

91

4.5.2 VISA-2 Loopback Test

Teridian used the ICT-K test lab in Korea (listed on the

www.emvco.com

website) for VISA-2 loopback

testing. This lab used the VISA test suite version 4.1 for their EMV Level I qualification test services
(details shown in

Figure 15

). The USB CCID firmware includes the source code that implements this

test.

Initialization

Enter Delay Time

(in Secs)

Power-Up Ok
(Good ATR)?

SELECT FILE

1PAY.SYS.DDF01

EMV Power

Down

M/m

Any other Key

Warm Reset OK?

Yes

No

No

Exchange OK?

End of Record?

or No Record?

Enter (M/m) Multi-
or (anykey) Single

Shot?

Delay Time Wait

EMV Power Up

Negotiable Mode?

No

PPS OK?

Yes

SingleShot?

Yes

No

No

Yes

No

Yes

READ RECORD

(00 B2 'P1' 0C 00)

Yes

P1 = 01

Increment RECORD

Index (P1)

Yes

No

Exchange OK?

No

T-AID Present

T-Select AID Command

Yes

Yes

Exchange OK?

No

Yes

No

T-Book1 - 12.4 Step 1

T - 00A404000CA00000000310100000000001

Figure 15: VISA-2 Loopback Test Flow Chart