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Pin definitions, Pinouts – Cypress Perform nvSRAM User Manual

Page 3

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PRELIMINARY

CY14B102L, CY14B102N

Document #: 001-45754 Rev. *B

Page 3 of 24

Figure 3. Pin Diagram - 54 Pin TSOP II (x16)

Pin Definitions

Pin Name

IO Type

Description

A

0

– A

17

Input

Address Inputs Used to Select one of the 262,144 bytes of the nvSRAM for x8 Configuration.

A

0

– A

16

Address Inputs Used to Select one of the 131,072 words of the nvSRAM for x16 Configuration.

DQ

0

– DQ

7

Input/Output Bidirectional Data IO Lines for x8 Configuration. Used as input or output lines depending on

operation.

DQ

0

– DQ

15

Bidirectional Data IO Lines for x16 Configuration. Used as input or output lines depending on

operation.

WE

Input

Write Enable Input, Active LOW. When selected LOW, data on the IO pins is written to the specific

address location.

CE

Input

Chip Enable Input, Active LOW. When LOW, selects the chip. When HIGH, deselects the chip.

OE

Input

Output Enable, Active LOW. The active LOW OE input enables the data output buffers during read

cycles. IO pins are tri-stated on deasserting OE HIGH.

BHE

Input

Byte High Enable, Active LOW. Controls DQ

15

- DQ

8

.

BLE

Input

Byte Low Enable, Active LOW. Controls DQ

7

- DQ

0

.

V

SS

Ground

Ground for the Device. Must be connected to the ground of the system.

V

CC

Power Supply Power Supply Inputs to the Device.

HSB

[7]

Input/Output Hardware Store Busy (HSB). When LOW this output indicates that a hardware store is in progress.

When pulled LOW external to the chip it initiates a nonvolatile STORE operation. A weak internal pull

up resistor keeps this pin HIGH if not connected (connection optional). After each store operation HSB

will be driven HIGH for short time with standard output high current.

V

CAP

Power Supply AutoStore Capacitor. Supplies power to the nvSRAM during power loss to store data from SRAM to

nonvolatile elements.

NC

No Connect No Connect. This pin is not connected to the die.

Pinouts

(continued)

NC

DQ7

DQ6

DQ5

DQ4

V

CC

DQ3

DQ2

DQ1

DQ0

NC

A

0

A

1

A

2

A

3

A

4

A

5

A

6

A

7

V

CAP

WE

A

8

A

10

A

11

A

12

A

13

A

14

A

15

A

16

1

2
3
4

5
6
7
8
9
10
11
12

13
14

15

16
17
18
19

20

21
22
23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

OE

CE

V

CC

NC

V

SS

NC

A

9

NC

NC

NC

NC

NC

NC

54
53
52
51

49

50

HSB

BHE

BLE

DQ15

DQ14
DQ13
DQ12

V

SS

DQ11
DQ10

DQ9
DQ8

(x16)

[6]

[4]

[5]

(Not to Scale)

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