Cypress Perform nvSRAM - Manual (Page 14)

PRELIMINARY
CY14B102L, CY14B102N
Document #: 001-45754 Rev. *B Page 14 of 24
Hardware STORE Cycle
Parameters Description
20 ns 25 ns 45 ns
Unit
Min Max Min Max Min Max
t
DHSB
HSB To Output Active Time when write latch not set 20 25 25 ns
t
PHSB
Hardware STORE Pulse Width 15 15 15 ns
t
SS
[28, 29] Soft Sequence Processing Time 100 100 100 μs
Switching Waveforms
Figure 14. Hardware STORE Cycle [22]
Figure 15. Soft Sequence Processing [28, 29]
W
3+6%
W
3+6%
W
'(/$<
W
'+6%
W
'(/$<
W
6725(
W
+++'
W
/=+6%
:ULWHODWFKVHW
:ULWHODWFKQRWVHW
+6%,1
+6%287
'4'DWD2XW
5:,
+6%,1
+6%287
5:,
+6%SLQLVGULYHQKLJKWR9
&&
RQO\E\,QWHUQDO
65$0LVGLVDEOHGDVORQJDV+6%,1LVGULYHQORZ
+6%GULYHULVGLVDEOHG
W
'+6%
N2KPUHVLVWRU
$GGUHVV $GGUHVV $GGUHVV $GGUHVV
6RIW6HTXHQFH
&RPPDQG
W
66
W
66
&(
$GGUHVV
9
&&
W
6$
W
&:
6RIW6HTXHQFH
&RPPDQG
W
&:
Notes
28. This is the amount of time it takes to take action on a soft sequence command. Vcc power must remain HIGH to effectively register command.
29. Commands such as STORE and RECALL lock out IO until operation is complete which further increases this time. See the specific command.
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