Cypress Perform nvSRAM - Manual (Page 2)

PRELIMINARY
CY14B102L, CY14B102N
Document #: 001-45754 Rev. *B Page 2 of 24
Pinouts
Figure 1. Pin Diagram - 48 FBGA
Figure 2. Pin Diagram - 44 Pin TSOP II
48-FBGA
(not to scale)
Top View
(x8)
48-FBGA
(not to scale)
Top View
(x16)
WE
V
CC
A
11
A
10
V
CAP
A
6
A
0
A
3
CE
NC
NC
DQ0
A
4
A
5
NC
DQ2
DQ3
NC
V
SS
A
9
A
8
OE
V
SS
A
7
NC NC
NC
A
17
A
2
A
1
NC
V
CC
DQ4 NC
DQ5
DQ6
NC DQ7
NC
A
15
A
14
A
13
A
12
HSB
3 2 6 5 4 1
D
E
B
A
C
F
G
H
A
16
NC
DQ1
NC
[6]
[4] [5]
WE
V
CC
A
11
A
10
V
CAP
A
6
A
0
A
3 CE
DQ10
DQ8
DQ9
A
4
A
5
DQ13
DQ12
DQ14
DQ15
V
SS
A
9
A
8
OE
V
SS
A
7
DQ0 BHE
NC
NC
A
2
A
1
BLE
V
CC
DQ2 DQ1
DQ3
DQ4
DQ5 DQ6
DQ7
A
15
A
14
A
13
A
12
HSB
3 2 6 5 4 1
D
E
B
A
C
F
G
H
A
16
NC NC
DQ11
[6] [5]
[4]
Notes
4. Address expansion for 4 Mbit. NC pin not connected to die.
5. Address expansion for 8 Mbit. NC pin not connected to die.
6. Address expansion for 16 Mbit. NC pin not connected to die.
7. HSB pin is not available in 44-TSOP II (x16) package.
44-TSOP II
(x16)
44-TSOP II
(x8) [7]
NC
A
8
NC
NC
V
SS
DQ6
DQ5
DQ4
V
CC
A
13
DQ3
A
12
DQ2
DQ1
DQ0
OE
A
9
CE
NC
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
11
A
7
A
14
A
15
A
16
A
17
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
A
10
NC
WE
DQ7
HSB NC
V
SS
V
CC
V
CAP
NC
(x8)
[6]
[4]
[5]
V
SS
DQ6
DQ5
DQ4
V
CC
A
13
DQ3
A
12
DQ2
DQ1
DQ0
BLE
A
9
CE
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8 A
11
A
10
A
14
BHE
OE
A
15
A
16
NC 1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
WE
DQ7
A
0
V
SS
V
CC
DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
DQ9
DQ8
V
CAP
(x16)
[4]
(Not to Scale)
(Not to Scale)
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