Cypress CY7C1350G - Manual (Page 15)

CY7C1350G
Document #: 38-05524 Rev. *F Page 15 of 15
Document History Page
Document Title: CY7C1350G 4-Mbit (128K x 36) Pipelined SRAM with NoBL™ Architecture
Document Number: 38-05524
REV. ECN NO.
Issue
Date Orig. of
Change Description of Change
** 224380 See ECN RKF New data sheet
*A 276690 See ECN VBL Changed TQFP pkg to lead-free TQFP in Ordering Info section
Added comment of BG lead-free package availability
*B 332895 See ECN SYT Converted from Preliminary to Final
Removed 225 MHz and 100 MHz speed grades
Address Expansion balls in the pinouts for 119 BGA Package was modified as per
JEDEC standards
Modified V
OL,
V
OH
test conditions
Replaced TBDs for
Θ
JA
and
Θ
JC
to their respective values on the Thermal Resistance
table
Changed the package name for 100 TQFP from A100RA to A101
Removed comment on the availability of BG lead-free package
Updated Ordering Information by removing Shaded Parts
*C 351194 See ECN PCI Updated Ordering Information Table
*D 419264 See ECN RXU Converted from Preliminary to Final
Changed address of Cypress Semiconductor Corporation on Page# 1 from “3901
North First Street” to “198 Champion Court”
Modified test condition from V
DDQ
< V
DD
to V
DDQ
< V
DD
Modified test condition from V
IH
< V
DD
to V
IH
< V
DD
Modified “Input Load” to “Input Leakage Current except ZZ and MODE” in the
Electrical Characteristics Table
Replaced Package Name column with Package Diagram in the Ordering Information
table
Replaced Package Diagram of 51-85050 from *A to *B
Updated the Ordering Information
*E 419705 See ECN RXU Added 100 MHz speed grade
*F 480368 See ECN VKN Added the Maximum Rating for Supply Voltage on V
DDQ
Relative to GND.
Updated the Ordering Information table.
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