Digilent 410-258P-KIT - Manual (Page 8)

Anvyl Reference Manual
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A VGA controller circuit must generate the HS and VS timings signals and coordinate the delivery of
video data based on the pixel clock. The pixel clock defines the time available to display one pixel of
information. The VS signal defines the “refresh” frequency of the display, or the frequency at which all
information on the display is redrawn. The minimum refresh frequency is a function of the display’s
phosphor and electron beam intensity, with practical refresh frequencies falling in the 50Hz to 120Hz
range. The number of lines to be displayed at a given refresh frequency defines the horizontal
“retrace” frequency. For a 640-pixel by 480-row display using a 25MHz pixel clock and 60 +/-1Hz
refresh, the signal timings shown in the table below can be derived. Timings for sync pulse width and
front and back porch intervals (porch intervals are the pre- and post-sync pulse times during which
information cannot be displayed) are based on observations taken from actual VGA displays.
A VGA controller circuit decodes the output of a horizontal-sync counter driven by the pixel clock to
generate HS signal timings. This counter can be used to locate any pixel location on a given row.
Likewise, the output of a vertical-sync counter that increments with each HS pulse can be used to
generate VS signal timings, and this counter can be used to locate any given row. These two
continually running counters can be used to form an address into video RAM. No time relationship
between the onset of the HS pulse and the onset of the VS pulse is specified, so the designer can
arrange the counters to easily form video RAM addresses, or to minimize decoding logic for sync
pulse generation.
T
S
T
disp
T
pw
T
fp
T
bp
T
S
T
disp
T
pw
T
fp
T
bp
Sync pulse time
Display time
VS pulse width
VS front porch
VS back porch
16.7ms
15.36ms
64 us
320 us
928 us
416,800
384,000
1,600
8,000
23,200
521
480
2
10
29
Symbol Parameter
Time Clocks Lines
Vertical Sync
32 us
25.6 us
3.84 us
640 ns
1.92 us
800
640
96
16
48
Clocks
Horizontal Sync
Time
Fig. 6. VGA sync signal timings.
Fig. 7. VGA display controller block diagram.
Audio (I
2
S)
The Anvyl board includes an Analog Devices audio codec SSM2603CPZ (IC5) with four 1/8” audio
jacks for line-out (J7), headphone-out (J6), line-in (J9), and microphone-in (J8).