Cypress Perform CY7C1513KV18 - Manual (Page 3)

CY7C1511KV18, CY7C1526KV18
CY7C1513KV18, CY7C1515KV18
Document Number: 001-00435 Rev. *E Page 3 of 31
Logic Block Diagram (CY7C1513KV18)
Logic Block Diagram (CY7C1515KV18)
CLK
A
(19:0)
Gen.
K
K
Control
Logic
Address
Register
D
[17:0]
Read Add. D
ecod
e
Read Data Reg.
RPS
WPS
Control
Logic
Address
Register
Reg.
Reg.
Reg.
36
20
72
18
BWS
[1:0]
V
REF
W
rite Add. De
code
Write
Reg
36
A
(19:0)
20
18
CQ
CQ
DOFF
Q
[17:0]
18
18
18
Write
Reg
Write
Reg
Write
Reg
C
C
1M x
1
8
Array
1M x
1
8
Array
1M x
1
8
Array
1M x
1
8
Array
18
51
2K x 36 Arra
y
CLK
A
(18:0)
Gen.
K
K
Control
Logic
Address
Register
D
[35:0]
Read Add.
Deco
de
Read Data Reg.
RPS
WPS
Control
Logic
Address
Register
Reg.
Reg.
Reg.
72
19
144
36
BWS
[3:0]
V
REF
W
rite Add. D
ecod
e
Write
Reg
72
A
(18:0)
19
51
2K x 36 Arra
y
51
2K x 36 Arra
y
51
2K x 36 Arra
y
36
CQ
CQ
DOFF
Q
[35:0]
36
36
36
Write
Reg
Write
Reg
Write
Reg
C
C
36
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