Cirrus Logic CS5480 - Manual (Page 19)

CS5480
DS980F3 19
4.8.1 Fixed Number of Samples Averaging
N is the preset value in the SampleCount register and
should not be set less than 100. By default, the Sample-
Count is 4000. With MCLK = 4.096MHz, the averaging
period is fixed at N/4000 = 1 second, regardless of the
line frequency.
4.8.2 Line-cycle Synchronized Averaging
When operating in Line-cycle Synchronized Averaging
mode, and when line frequency measurement is
enabled (see section
5.4 Line Frequency Measurement
on page 22), the CS5480 uses the voltage (V) channel
zero crossings and measured line frequency to
automatically adjust N such that the averaging period
will be equal to the number of half line-cycles in the
CycleCount register. For example, if the line frequency
is 51Hz, and the CycleCount register is set to 100,
N will be 4000

(100/2)/51 = 3921 during continuous
conversion. N is self-adjusted according to the line
frequency; therefore, the averaging period is always
close to the whole number of half line-cycles, and the
low-rate calculation results will minimize ripple and
maximize resolution, especially when the line frequency
varies. Before starting a low-rate conversion in
Line-cycle Synchronized Averaging mode, the
SampleCount register should not be changed from its
default value of 4000, and bit AFC of the Config2
register must be set. During continuous conversion, the
host processor should not change the SampleCount
register.
4.8.3 RMS Current and Voltage
The root mean square (RMS in Figure 11) calculations
are performed on N instantaneous current and voltage
samples using Equation 1:
4.8.4 Active Power
The instantaneous voltage and current samples are
multiplied to obtain the instantaneous power (P1, P2)
(see
Figures 9 and 11 ). The product is then averaged
over N samples to compute active power (P1
AVG
,
P2
AVG
).
4.8.5 Reactive Power
Instantaneous reactive power (Q1, Q2) are sample rate
results obtained by multiplying instantaneous current
(I1, I2) by instantaneous quadrature voltage
(V1Q, V2Q), which are created by phase shifting the
instantaneous voltage (V1, V2) 90 degrees using
first-order integrators (see
Figures 9 and 11 ). The gain
of these integrators is inversely related to line
frequency, so their gain is corrected by the Epsilon
register, which is based on line frequency. Reactive
power (Q1
AVG
, Q2
AVG
) is generated by integrating the
instantaneous quadrature power over N samples.
4.8.6 Apparent Power
By default, the CS5480 calculates the apparent power
(S1, S2) as the product of RMS voltage and current as
shown in Equation 2:
The CS5480 also provides an alternate apparent power
calculation method, which uses real power (P1
AVG
,
P2
AVG
) and reactive power (Q1
AVG
, Q2
AVG
) to calcu-
late apparent power, as shown in Equation 3:
The APCM bit in the Config2 register controls which
method is used for apparent power calculation.
4.8.7 Peak Voltage and Current
Peak current (I1
PEAK
, I2
PEAK
) and peak voltage
(V
PEAK
) are calculated over N samples and recorded in
the corresponding channel peak register documented in
the register map. This peak value is updated every N
samples.
4.8.8 Power Factor
Power factor (PF1, PF2) is active power divided by ap-
parent power as shown in Equation 4. The sign of the
power factor is determined by the active power.
4.9 Average Active Power Offset
The average active power offset registers, P1
OFF
(P2
OFF
), can be used to offset erroneous power sources
resident in the system not originating from the power
line. Residual power offsets are usually caused by
crosstalk into current channels from voltage channels,
or from ripple on the meter’s or chip’s power supply, or
from inductance from a nearby transformer.
IRMS
In
2
n 0 =
N 1 –

N
--------------------
= VRMS
Vn
2
n 0 =
N 1 –

N
----------------------
= [Eq. 1]
S V
RMS
I
RMS
 = [Eq. 2]
S Q
AVG
2 P
AVG
2 + =
[Eq. 3]
PF
P
ACTIVE
S
---------------------- =
[Eq. 4]