Cirrus Logic CS5372A - Manual (Page 28)

CS5371A CS5372A
28 DS748F3
VREF+
_
Positive Voltage Reference Input, pin 5
Input for an external +2.5 V voltage reference relative to VREF-.
VREF-
_
Negative Voltage Reference Input, pin 6
This pin should be tied to VA- near the voltage reference output.
Digital Inputs
MCLK
_
Modulator Clock Input, pin 19
A CMOS compatible clock input for the modulator internal master clock, nominally 2.048 MHz
with an amplitude equal to the VD digital power supply.
MSYNC
_
Modulator Sync Input, pin 20
A low to high transition resets the internal clock phasing of the modulator. This assures the
sampling instant and modulator data output are synchronous to the external system.
OFST
_
Offset Mode Select, pin 14
When high, adds approximately -60 mV or -35 mV of internal differential offset to the analog
input signal to guarantee any
ΔΣ idle tones are removed. When low, no offset is added.
PWDN1, PWDN2
_
Channel 1 & 2 Power-down Mode, pin 24, 13
When high, the modulator is in power down mode. Halting MCLK while in power down mode
reduces modulator power dissipation further.
Digital Outputs
MDATA1, MDATA2
_
Modulator Data Output, pin 21, 16
Modulator data is output as a 1-bit serial data stream at 512 kHz with an MCLK input of
2.048 MHz.
MFLAG1, MFLAG2
_
Modulator Flag, pin 22, 15
A high level output indicates the modulator is unstable due to an over-range on the analog
inputs.