Cirrus Logic CS5372A - Manual (Page 21)

CS5371A CS5372A
DS748F3 21
7. VOLTAGE REFERENCE
The CS5371A and CS5372A modulators re-
quire a 2.500 V precision voltage reference to
be supplied to the VREF
± pins.
7.1 VREF Power Supply
To guarantee proper regulation headroom for
the voltage reference device, the voltage refer-
ence GND pin should be connected to VA- in-
stead of system ground, as shown in
Figure 14 . This connection results in a VREF-
voltage equal to VA- and a VREF+ voltage
very near ground [(VA-) + 2.500 VREF].
Power supply inputs to the voltage reference
device should be bypassed to system ground
with 0.1
μF capacitors placed as close as pos-
sible to the power and ground pins. In addition
to 0.1
μF local bypass capacitors, at least
100
μF of bulk capacitance to system ground
should be placed on each power supply near
the voltage regulator outputs. Bypass capaci-
tors should be X7R, C0G, tantalum, or other
high-quality dielectric type.
7.2 VREF RC Filter
A primary concern in selecting a precision volt-
age reference device is noise performance in
the measurement bandwidth. The
Linear
Technology LT1019AIS8-2.5 voltage refer-
ence yields acceptable noise levels if the out-
put is filtered with a low-pass RC filter.
A separate RC filter is required for each sys-
tem device connected to a given voltage refer-
ence output. By sharing a common RC filter,
signal-dependent sampling of the voltage ref-
erence by one system device could cause un-
wanted tones to appear in the measurement
bandwidth of another system device via com-
mon impedance coupling.
7.3 VREF PCB Routing
To minimize the possibility of outside noise
coupling into the CS5371A and CS5372A volt-
age reference input, the VREF
± traces should
be routed as a differential pair from the large
capacitor of the voltage reference RC filter.
Careful control of the voltage reference source
and return currents by routing VREF
± as a dif-
ferential pair will significantly improve immuni-
ty from external noise.
To further improve noise rejection of the
VREF
± differential route, include 0.1
μF by-
pass capacitors to system ground as close as
possible to the VREF+ and VREF- pins of the
CS5371A and CS5372A.
7.4 VREF Input Impedance
The switched-capacitor input architecture of
the VREF
± inputs results in an input imped-
ance that depends on the internal capacitor
size and the MCLK frequency. With a 15 pF in-
ternal capacitor and a 2.048 MHz MCLK, the
VREF input impedance is approximately
1 / [(2.048 MHz) x (15 pF)] = 32 k
Ω. While the
size of the internal capacitor is fixed, the volt-
10
Ω
To VREF+
+
From VA+
Regulator
2.500 V
VREF
0.1 μF
To VREF-
0.1 μF 100 μF
0.1 μF
0.1 μF
0.1 μF
100 μF
100 μF
From VA-
Regulator
Route VREF ± as a differential pair
from the 100uF RC filter capacitor
Figure 14. Voltage Reference Circuit