Cirrus Logic CS5372A - Manual (Page 18)

CS5371A CS5372A
18 DS748F3
5. DIGITAL SIGNALS
The CS5371A and CS5372A modulators are
designed to operate with the CS5376A digital
filter. The digital filter generates the modulator
clock and synchronization signals (MCLK and
MSYNC) while receiving back the modulator
one-bit
ΔΣ conversion data and over-range
flag (MDATA and MFLAG).
5.1 MCLK Connection
The CS5376A digital filter generates the mas-
ter clock for CS5371A and CS5372A, typically
2.048 MHz, from a synchronous clock input
from the external system. If MCLK is disabled
during operation, the modulators will enter a
power down state after approximately 40
µ S.
By default, MCLK is disabled at reset and is
enabled by writing the digital filter CONFIG
register.
MCLK must have low jitter to guarantee full an-
alog performance, requiring a crystal- or
VCXO-based system clock input to the digital
filter. Clock jitter on the digital filter CLK input
directly translates to jitter on MCLK.
5.2 MSYNC Connection
The CS5376A digital filter also provides a syn-
chronization signal to the CS5371A and
CS5372A modulators. The MSYNC signal is
automatically generated following a rising
edge received on the digital filter SYNC input.
By default, MSYNC generation is disabled at
reset and is enabled by writing the digital filter
CONFIG register.
The input SYNC signal to the CS5376A digital
filter sets a common reference time t
0
for mea-
surement events, thereby synchronizing ana-
log sampling across a measurement network.
The timing accuracy of the received SYNC sig-
nal from measurement node to measurement
node must be ±1 MCLK to maximize the
MSYNC analog sample synchronization accu-
racy.
CS5372A
ΔΣ Modulator
INF+
INR+
INF-
INR-
INF-
INR-
INF+
INR+
VREF+
VREF-
VA+
VA-
VD
GND
MDATA1
MFLAG1
MDATA2
MFLAG2
MCLK
MSYNC
PWDN1
OFST
PWDN2
VREF
2.5 V
VA+
VA-
10 Ω
0.01 μF
VD
CS5376A
Digital Filter
VDD2
GND
MDATA1
MFLAG1
MDATA2
MFLAG2
MCLK
MSYNC
GPIO
GPIO
GPIO
VA+
0.1 μF 0.01 μF
VD
VA-
0.1 μF
20nF
C0G
20nF
C0G
680
CS3301A
CS3302A
AMPLIFIER
OUTR+
OUTF+
OUTF-
OUTR-
680
680
680
20nF
C0G
20nF
C0G
680
CS3301A
CS3302A
AMPLIFIER
OUTR+
OUTF+
OUTF-
OUTR-
680
680
680
VA+
VA+
VA-
VA-
VA+
VA+
VA-
VA-
100 μF
Figure 12. Digital Signals