Cirrus Logic CS485xx - Manual (Page 95)

9-15 Copyright 2009 Cirrus Logic, Inc. DS734UM7
48-Pin LQFP Pin Assigments
CS485xx Hardware User’s Manual
Figure 9-11 shows the 48-Pin LQFP Pin Layout of the CS48540.
Figure 9-11. 48-Pin LQFP Pin Layout of CS48540
XTO
XTI
GNDA
PLL_REF_RES
VDDA (3.3V) GPIO1, DAI1_DATA2
GPIO2
GPIO
16,
D
AI
1_DAT
A
0
GPI
O
0,
DAI
1_DAT
A
1
38
40
41
42
43
45
46
GPIO13, SCP_BSY#, EE_CS#
GPOI12, SCP_IRQ#
GP
IO
10,
S
CP
__M
IS
O
/S
DA
G
P
IO
9,
SCP_MOSI
GPI
O
11,
S
CP_CLK
35 33 31 30 28 26 25
GN
D
4
GNDIO4
VDD3
GND3
VDDIO3
G
NDIO
3
23
22
21
19
17
15
1
GPIO5,
XMTA
GPIO3,
DAO1_
D
ATA1,
H
S1
DAO1_DATA0, HS0
DAO_LRCLK
DAI1_LRCLK
GP
IO
18
,D
AO
_M
C
LK
DA
I1
_SCLK
VDD1
GND1
DAO_SCLK
GPIO
4,
DAO
1_
D
ATA2,
H
S2
RESET
#
VDDI
O1
GNDI
O1
GPIO6,
DAO2_DATA0,
H
S3
GPIO7,
HS4
VDD
2
GND2
VDDIO2
GNDIO2
2 3 4 5 6 7 9 10 11 12
GPIO8, SCP_CS#
TE
S
T
DBDA DBCK
XTAL_OUT GPIO15, DAI2_SCLK
GPIO14, DAI2_LRCLK
GPIO17, DAI2_DATA0
CS48540
48 LQFP
8
13
14
16
18
20
24
27 29 32 34 36
37
39
44
47
48