Cirrus Logic CS485xx - Manual (Page 5)

DS734UM7 Copyright 2009 Cirrus Logic v
Figures
CS485xx Hardware User’s Manual
8.2.1.2 Ground .........................................................................................................8-11
8.2.1.3 Decoupling ...................................................................................................8-11
8.2.2 PLL Filter ......................................................................................................................8-11
8.2.2.1 Analog Power Conditioning .........................................................................8-11
8.2.3 PLL ...............................................................................................................................8-12
8.3 Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-12
8.4 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-13
8.4.1 Operational Mode .........................................................................................................8-13
8.5 48-Pin LQFP Pin Assigments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-15
8.6 Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-18
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-22
Figures
Figure 1-1. CS48560 Chip Functional Block Diagram ..................................................................................1-2
Figure 1-2. CS48540 Chip Functional Block Diagram ..................................................................................1-3
Figure 1-3. CS48520 Chip Functional Block Diagram ..................................................................................1-4
Figure 2-1. Operation Mode Block Diagrams ...............................................................................................2-1
Figure 2-2. Slave Boot Sequence ................................................................................................................2-4
Figure 2-3. Master Boot Sequence Flowchart ..............................................................................................2-7
Figure 2-4. Soft Boot Sequence Flowchart ..................................................................................................2-9
Figure 2-5. Soft Boot Example Flowchart ...................................................................................................2-10
Figure 2-6. Flowchart of Steps Used to Exit Low Power Mode ..................................................................2-13
Figure 3-1. Serial Control Port Internal Block Diagram ................................................................................3-2
Figure 3-2. Block Diagram of I
2
C System Bus .............................................................................................3-3
Figure 3-3. I
2
C Start and Stop Conditions ....................................................................................................3-4
Figure 3-4. I
2
C Address with ACK and NACK ..............................................................................................3-5
Figure 3-5. Data Byte with ACK and NACK .................................................................................................3-6
Figure 3-6. Stop Condition with ACK and NACK ..........................................................................................3-6
Figure 3-7. Repeated Start Condition with ACK and NACK .........................................................................3-7
Figure 3-8. I
2
C Write Flow Diagram .............................................................................................................3-8
Figure 3-9. I
2
C Read Flow Diagram ...........................................................................................................3-10
Figure 3-10. Sample Waveform for I
2
C Write Functional TIming ...............................................................3-12
Figure 3-11. Sample Waveform for I
2
C Read Functional Timing ...............................................................3-12
Figure 3-12. SPI Serial Control Port Internal Block Diagram .....................................................................3-13
Figure 3-13. Block Diagram of SPI System Bus .........................................................................................3-15
Figure 3-14. SPI Address and Data Bytes .................................................................................................3-16
Figure 3-15. SPI Write Flow Diagram .........................................................................................................3-18
Figure 3-16. SPI Read Flow Diagram ........................................................................................................3-19
Figure 3-17. Sample Waveform for SPI Write Functional Timing ...............................................................3-21