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2 clock and data flow for s/pdif input, 2 clock and data flow for s/pdif input -15, Figure 1-9. s/pdif clocking -15 – Cirrus Logic CDB470xx User Manual

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Copyright 2014 Cirrus Logic, Inc.

DS886DB11

Audio Clocking
CDB47xxx User’s Manual

1.5.2 Clock and Data Flow for S/PDIF Input

Figure 1-9. S/PDIF Clocking

The S/PDIF clocking architecture is used when any S/PDIF RX is used as an audio source, whether from
the optical RX, coaxial RX, or brought in on the DAI header.

Figure 1-9

illustrates this clocking

configuration.

The incoming S/PDIF stream is always rate matched to another MCLK in the system through an SRC.
This means that the DAO can be run at a constant Fs that is independent of the incoming S/PDIF Fs. This
is useful in systems with digital amplifiers and wireless audio transmitter modules that requires a fixed Fs.

The CS470xx can master its output clocks, or slave to clocks from another source.

See also other documents in the category Cirrus Logic Hardware: