Cirrus Logic CS4224 - Manual (Page 11)

CS4223 CS4224
DS290F1 11
SWITCHING CHARACTERISTICS - CONTROL PORT - I
2
C MODE (CS4224)
(Inputs: Logic 0 = DGND, Logic 1 = VD; C
L
= 30 pF)
Notes: 15. Not tested but guaranteed by design.
16. Data must be held for sufficient time to bridge the 300 ns transition time of SCL.
Parameter Symbol Min Max Unit
I
2
C
®
Mode (SPI/I2C = 1)
SCL Clock Frequency f
scl
- 100 kHz
RST rising edge to Start (Note 15) t
irs
50 - µs
Bus Free Time between transmissions t
buf
4.7 - µs
Start Condition Hold Time (prior to first clock pulse) t
hdst
4.0 - µs
Clock Low Time t
low
4.7 - µs
Clock High Time t
high
4.0 - µs
Setup time for repeated Start Condition t
sust
4.7 - µs
SDA hold time for SCL falling (Note 16) t
hdd
0 - µs
SDA setup time to SCL rising t
sud
250 - ns
Rise time of SCL t
rc
- 25 ns
Fall time of SCL t
fc
- 25 ns
Rise time of SDA t
rd
- 1 µs
Fall time of SDA t
fd
- 300 ns
Setup time for Stop Condition t
susp
4.7 - µs
t
buf t hdst
t
hdst
t
low
t rc
t fc
t
hdd
t high
t sud t sust
t susp
Stop Start Start Stop
Repeated
SDA
SCL
t
irs
RST
t rd t fd
Figure 3. I
2
C Control Port Timing