AMD Socket AM2+ Quad Core AMD Processor SB750 - Manual (Page 31)

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3-6-1 Memory Configuration
CMOS Setup Utility-Copyright(C)1985-2005 American Megatrends. Inc.
Memory Configuration
Help Item DRAM Timing Mode Auto
Memory CLK: 400MHz
CAS Latency (Tcl): 5.0
RAS/CAS Delay(Trcd): 5CLK
Row Precharge Time(Trp): 5 clk
Min Active RAS(Trrd): 3CLK
Row Cycle(Trc) 23 CLK
Write Recover Time(Twr) 6 CLK
Bank Interleaving Auto
Enabled clock to AC1 DIMMs Disabled
Mem CLK Tristate C3/ATL VID Disabled
Memory Hole Remapping Enabled
DCI Unganged Mode Always
Power Down Enabled Enabled
Power Down Mode Channel
Options
Auto
DCT0
↑↓→← Move Enter:Select +/-/PU/PD:Value F10:Save ESC:Exit F1:General Help
F5:Previous Values F6:Optimized Defaults F7:Standard Defaults
Bank Interleaving
Use this item to enable bank memory interleaving.
Enable Clock to ALL DIMMs
Enable unused clocks to DIMMS when memory slots are not populated.
Mem CLK Tristate during C3 and Alt VID.
Enable and disable Mem CLK Tri-stating during C3 and Alt VID
Memory Hole Remapping
Enable Memory Remapping around Memory Hole.
DCT Unganged Mode
This allows selection of unganged DRAM MODE (64- bit width).
Auto=Ganged Mode; Always= Unganged Mode.
Power Down Enable
Enable or Disable power down mode.
Power Down Mode
Set the DDR power down mode. The optional settings are Channel; Chipset.