Analog Devices ADSP-2181 User Manual
Page 22
ADSP-2181/ADSP-2183
REV. 0
–22–
ADSP-2181/ADSP-2183
Parameter
Min
Max
Unit
Bus Request/Grant
Timing Requirements:
t
BH
BR
Hold after CLKOUT High
1
0.25t
CK
+ 2
ns
t
BS
BR
Setup before CLKOUT Low
1
0.25t
CK
+ 17
ns
Switching Characteristics:
t
SD
CLKOUT High to xMS,
0.25t
CK
+ 10
ns
RD
, WR Disable
t
SDB
xMS
, RD, WR
Disable to BG Low
0
ns
t
SE
BG
High to xMS,
RD
, WR Enable
0
ns
t
SEC
xMS
, RD, WR
Enable to CLKOUT High
0.25t
CK
– 7
ns
t
SDBH
xMS
, RD, WR
Disable to BGH Low
2
0
ns
t
SEH
BGH
High to xMS,
RD
, WR Enable
2
0
ns
NOTES
xMS
= PMS, DMS, CMS, IOMS, BMS
1
BR
is an asynchronous signal. If BR meets the setup/hold requirements, it will be recognized during the current clock cycle; otherwise the signal will be recognized on
the following cycle. Refer to the ADSP-2100 Family User’s Manual for BR/BG cycle relationships.
2
BGH
is asserted when the bus is granted and the processor requires control of the bus to continue.
CLKOUT
t
SD
t
SDB
t
SE
t
SEC
t
SDBH
t
SEH
t
BS
BR
t
BH
CLKOUT
PMS
,
DMS
BMS
,
RD
WR
BG
BGH
Figure 24. Bus Request–Bus Grant