Analog Devices ADSP-2181 - Manual (Page 20)

ADSP-2181/ADSP-2183
REV. 0 –20–
ADSP-2181
Parameter Min Max Unit
Clock Signals and Reset
Timing Requirements:
t
CKI
CLKIN Period 60 150 ns
t
CKIL
CLKIN Width Low 20 ns
t
CKIH
CLKIN Width High 20 ns
Switching Characteristics:
t
CKL
CLKOUT Width Low 0.5t
CK
– 7 ns
t
CKH
CLKOUT Width High 0.5t
CK
– 7 ns
t
CKOH
CLKIN High to CLKOUT High 0 20 ns
Control Signals
Timing Requirements:
t
RSP
RESET Width Low 5t
CK
1 ns
ADSP-2183
28.8 MHz
Parameter Min Max Unit
Clock Signals and Reset
Timing Requirements:
t
CKI
CLKIN Period 69.4 150 ns
t
CKIL
CLKIN Width Low 20 ns
t
CKIH
CLKIN Width High 20 ns
Switching Characteristics:
t
CKL
CLKOUT Width Low 0.5t
CK
– 7 ns
t
CKH
CLKOUT Width High 0.5t
CK
– 7 ns
t
CKOH
CLKIN High to CLKOUT High 0 20 ns
Control Signals
Timing Requirements:
t
RSP
RESET Width Low 5t
CK
1 ns
NOTE
1 Applies after power-up sequence is complete. Internal phase lock loop requires no more than 2000 CLKIN cycles assuming stable CLKIN (not including crystal
oscillator start-up time).
CLKIN
CLKOUT
t
CKIL
t
CKOH
t
CKH
t
CKL
t
CKI
t
CKIH
Figure 22. Clock Signals