Table 14-27 – ARM Cortex R4F User Manual
Page 397
Cycle Timings and Interlock Behavior
ARM DDI 0363E
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14.22 Floating-point double-precision data processing instructions
This section describes the cycle timing behavior for all double-precision VFP
CDP
instructions.
This includes arithmetic instructions such as
VMUL.F64
, data and immediate moving instructions
such as
“VMOV.F64
”,
VABS.F64
,
VNEG.F64
, and
“VMOV
, and comparison
instructions and conversion instructions.
Table 14-27 shows the floating-point double-precision data processing instructions cycle timing
behavior
Table 14-27 Floating-point double-precision data processing instructions cycle timing
behavior
Example instruction
Cycles
Early Reg
Result latency
VMLA.F64
a
a. Also
VMLS.F64
,
VNMLS.F64
, and
VNMLA.F64
.
13
,
19
VADD.F64
b
b. Also
VSUB.F64
,
VMUL.F64
, and
VNMUL.F64
.
3
,
9
VDIV.F64
3
,
96
VSQRT.F64
3
96
VMOV.F64
1
-
1
VMOV.F64
c
c. Also
VABS.F64
and
VNEG.F64
.
1
-
1
VCMP.F64
d
d. Also
VCMPE.F64
.
2
,
-
VCMPE.F64
2
-
VCVT.F64.U32
e
e. Also
VCVT.F64.S32
.
3
7
VCVT.F64.U32
f
f. Also
VCVT.F64.U16
,
VCVT.F64.S32
, and
VCVT.F64.S16
.
3
7
VCVTR.U32.F64
g
g. Also
VCVT.U32.F64
,
VCVTR.S32.F64
, and
VCVT.S32.F64
.
3
7
VCVT.U32.F64
h
h. Also
VCVT.U16.F64
,
VCVT.S32.F64
, and
VCVT.S16.F64
.
3
7
VCVT.F32.F64
3
7