ARM Cortex R4F - Manual (Page 174)

Events and Performance Monitor
ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 6-10
ID013010 Non-Confidential, Unrestricted Access
Figure 6-3 CNTENC Register format
Table 6-4 shows how the bit values correspond with the CNTENC Register.
To access the CNTENC Register, read or write CP15 with:
MRC p15, 0, , c9, c12, 2 ; Read CNTENC Register
MCR p15, 0, , c9, c12, 2 ; Write CNTENC Register
Writing to bits in this register disables individual counters, and clears the corresponding bits in
the CNTENS Register, see c9, Count Enable Set Register on page 6-8.
You can use the enable, EN, bit [0] of the PMNC Register to disable all performance counters
including CCNT, see c9, Performance Monitor Control Register on page 6-7.
The CNTENC and CNTENS Registers retain their values when the enable bit of the PMNC is
clear, even though their settings are ignored. The CNTENC Register can be used to clear the
enabled flags for individual counters even when all counters are disabled in the PMNC Register.
6.3.4 c9, Overflow Flag Status Register
The overflow FLAG status (FLAG) Register indicates if performance monitor counters have
overflowed.
The FLAG Register is:
• A read/write register
• Always accessible in Privileged mode. The USEREN Register determines accessibility in
User mode, see c9, User Enable Register on page 6-15.
Figure 6-4 on page 6-11 shows the bit arrangement for the FLAG Register.
C
31 3 2 1 0
Reserved
P2
P1
P0
Performance monitor
counter disables
Cycle count disable
Table 6-4 CNTENC Register bit functions
Bits Field Function
[31] C Cycle counter enable clear:
0 = disable
1 = enable.
[30:3] Reserved UNP on reads, SBZP on writes
[2] P2 Counter 2 enable
[1] P1 Counter 1 enable
[0] P0 Counter 0 enable