ARM Cortex R4F - Manual (Page 18)

Preface
ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. xviii
ID013010 Non-Confidential, Unrestricted Access
Read this for a description of the Memory Protection Unit (MPU) and the access
permissions process.
Chapter 8 Level One Memory System
Read this for a description of the Level One (L1) memory system.
Chapter 10 Power Control
Read this for a description of the power control facilities.
Chapter 11 Debug
Read this for a description of the debug support.
Chapter 12 FPU Programmer’s Model
Read this for a description of the Floating Point Unit (FPU) support in the
Cortex-R4F processor.
Chapter 13 Integration Test Registers
Read this for a description of the Integration Test Registers, and of integration
testing of the processor with an ETM-R4 trace macrocell.
Chapter 15 AC Characteristics
Read this for a description of the timing parameters applicable to the processor.
Chapter 14 Cycle Timings and Interlock Behavior
Read this for a description of the instruction cycle timing and instruction
interlocks.
Appendix A Processor Signal Descriptions
Read this for a description of the inputs and outputs of the processor.
Appendix B ECC Schemes
Read this for a description of how to select the Error Checking and Correction
(ECC) scheme depending on the Tightly-Coupled Memory (TCM) configuration.
Appendix C Revisions
Read this for a description of the technical changes between released issues of this
book.
Glossary Read this for definitions of terms used in this guide.
Conventions
Conventions that this book can use are described in:
•
Typographical
• Timing diagrams on page xix
• Signals on page xix.
Typographical
The typographical conventions are:
italic Highlights important notes, introduces special terminology, denotes
internal cross-references, and citations.
bold Highlights interface elements, such as menu names. Denotes signal
names. Also used for terms in descriptive lists, where appropriate.