Figure 4-9: clear cmos jumper, Table 4-3: clear cmos jumper settings – IEI Integration PICOe-HM650 User Manual
Page 70
PICOe-HM650 Half-size PCIe CPU Card
Page 56
If the “CMOS Settings Wrong” message is displayed during the boot up process, the fault
may be corrected by pressing the F1 to enter the CMOS Setup menu. Do one of the
following:
Enter the correct CMOS setting
Load Optimal Defaults
Load Failsafe Defaults.
After having done one of the above, save the changes and exit the CMOS Setup menu.
The clear CMOS jumper settings are shown in
7
Table 4-3.
Setting Description
Short 1 - 2
Keep CMOS Setup (Default)
Short 2 - 3
Clear CMOS Setup
Table 4-3: Clear CMOS Jumper Settings
The location of the clear CMOS jumper is shown in
7
Figure 4-9 below.
Figure 4-9: Clear CMOS Jumper
See also other documents in the category IEI Integration Hardware:
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- SPCIE-C2060 v1.01 (200 pages)
- SPCIE-C2060 v2.12 (212 pages)
- SPCIE-C2160 (204 pages)
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- PCIE-Q350 v1.00 (272 pages)
- PCIE-Q350 v1.12 (250 pages)
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- PCIE-Q350 v1.30 (213 pages)
- PCIE-Q57A (159 pages)
- PCIE-G41A2 (151 pages)
- PCIE-Q670 v1.03 (206 pages)
- PCIE-Q670 v2.00 (205 pages)
- PCIE-H610 (181 pages)
- PCIE-Q870-i2 (217 pages)
- IOWA-LX-600 (159 pages)
- PCISA-945GSE v1.01 (207 pages)
- PCISA-945GSE v1.10 (190 pages)
- PCISA-9652 v1.00 (232 pages)
- PCISA-9652 v1.01 (232 pages)
- PCISA-PV-D4251_N4551_D5251 (145 pages)
- PICOe-945GSE (197 pages)
- PICOe-GM45A (198 pages)
- PICOe-PV-D4251_N4551_D5251 v1.00 (154 pages)
- PICOe-PV-D4251_N4551_D5251 v1.10 (154 pages)
- PICOe-PV-D4251_N4551_D5251 v1.11 (155 pages)
- PICOe-B650 (156 pages)
- HYPER-KBN (139 pages)
- SPXE-14S (3 pages)
- SPXE-9S v1.00 (5 pages)
- SPXE-9S v1.1 (6 pages)
- SPE-9S v1.00 (4 pages)
- SPE-9S v1.1 (5 pages)
- SPE-6S (3 pages)
- SPE-4S (4 pages)
- PE-6SD3 (4 pages)
- PE-6SD2 v4.0 (4 pages)
- PE-6SD2 v2.10 (3 pages)
- PE-6SD (3 pages)
- PE-6S3 v1.0 (2 pages)
- PE-6S3 v4.0 (4 pages)
- PE-6S2 (4 pages)