GE Industrial Solutions 40A Digital MegaDLynx - Manual (Page 31)

GE
Data Sheet
40A Digital MegaDLynx TM : Non-Isolated DC-DC Power Modules
4.5Vdc –14.4Vdc input; 0.45Vdc to 2.0Vdc output; 40A Output Current
April 24, 2013 ©2012 General Electric Company. All rights reserved. Page 31
Example Application Circuit
Requirements:
Vin:
12V
Vout: 1.8V
Iout: 30A max., worst case load transient is from 20A to 30A
 Vout: 1.5% of Vout (27mV) for worst case load transient
Vin, ripple 1.5% of Vin (180mV, p-p)
CI1 Decoupling cap - 1x0.01  F/16V ceramic capacitor (e.g. Murata LLL185R71E103MA01)
CI2 3x22  F/16V ceramic capacitor (e.g. Murata GRM32ER61C226KE20)
CI3 470  F/16V bulk electrolytic
CO1 Decoupling cap - 1x0.01  F/16V ceramic capacitor (e.g. Murata LLL185R71E103MA01)
CO2 4 x 47µF/6.3V ceramic capacitor (e.g. Murata GRM31CR60J476ME19)
CO3 6 X330µF/6.3V Polymer (e.g. Sanyo Poscap)
CTune 5600pF ceramic capacitor (can be 1206, 0805 or 0603 size)
RTune 220 ohms SMT resistor (can be 1206, 0805 or 0603 size)
RTrim 10k  SMT resistor (can be 1206, 0805 or 0603 size, recommended tolerance of 0.1%)
Note: The DATA, CLK and SMBALRT pins do not have any pull-up resistors inside the module. Typically, the SMBus master
controller will have the pull-up resistors as well as provide the driving source for these signals.
RADDR0
DATA
CLK
VS-
RADDR1
GND
Vin+
CI3 CO3
ADDR0
VOUT
VS+
GND
TRIM
CTUNE
RTUNE
RTrim
VIN
CO1 CI1
Vout+
ON/OFF
SEQ
SMBALRT#
MODULE
PGOOD
ADDR1
SIG_GND
SYNC
CI2
CO2
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