Test configurations, Design considerations, Austin superlynx – GE Industrial Solutions Austin SuperLynx II 12V SMT User Manual
Page 10: Input filtering, Lineage power 10, Figure 24. output ripple and noise test setup

Data Sheet
October 1, 2009
Austin SuperLynx
TM
II
12V SMT Non-isolated Power Modules:
8.3 – 14Vdc Input; 0.75Vdc to 5.5Vdc Output;16A output current
LINEAGE
POWER
10
Test Configurations
TO OSCILLOSCOPE
CURRENT PROBE
L
TEST
1μH
B
A
TTE
R
Y
C
S
1000μF
Electrolytic
E.S.R.<0.1
Ω
@ 20°C 100kHz
2x100μF
Tantalum
V
IN
(+)
COM
NOTE: Measure input reflected ripple current with a simulated
source inductance (L
TEST
) of 1μH. Capacitor C
S
offsets
possible battery impedance. Measure current as shown
above.
C
IN
Figure 23. Input Reflected Ripple Current Test Setup.
NOTE: All voltage measurements to be taken at the module
terminals, as shown above. If sockets are used then
Kelvin connections are required at the module terminals
to avoid measurement errors due to socket contact
resistance.
V
O
(+)
COM
1uF
.
RESISTIVE
LOAD
SCOPE
COPPER STRIP
GROUND PLANE
10uF
Figure 24. Output Ripple and Noise Test Setup.
V
O
COM
V
IN
(+)
COM
R
LOAD
R
contact
R
distribution
R
contact
R
distribution
R
contact
R
contact
R
distribution
R
distribution
V
IN
V
O
NOTE: All voltage measurements to be taken at the module
terminals, as shown above. If sockets are used then
Kelvin connections are required at the module terminals
to avoid measurement errors due to socket contact
resistance.
Figure 25. Output Voltage and Efficiency Test Setup.
η =
V
O
. I
O
V
IN
. I
IN
x
100
%
Efficiency
Design Considerations
Input Filtering
Austin SuperLynx
TM
II 12V SMT module should be
connected to a low-impedance source. A highly
inductive source can affect the stability of the
module. An input capacitance must be placed
directly adjacent to the input pin of the module, to
minimize input ripple voltage and ensure module
stability.
In a typical application, 6x47 µF low-ESR tantalum
capacitors (AVX part #: TPSE476M025R0100, 47µF
25V 100 mΩ ESR tantalum capacitor) will be
sufficient to provide adequate ripple voltage at the
input of the module. To further minimize ripple
voltage at the input, very low ESR ceramic
capacitors are recommended at the input of the
module. Figure 26 shows input ripple voltage (mVp-
p) for various outputs with 6x47 µF tantalum
capacitors and with 6x22 µF ceramic capacitor (TDK
part #: C4532X5R1C226M) at full load.
Input
Ri
ppl
e
Vol
tage (m
Vp
-p
)
0
50
100
150
200
250
300
350
0
1
2
3
4
5
6
Tantalum
Ceramic
Output
Voltage
(Vdc)
Figure 26. Input ripple voltage for various output
with 6x47 µF tantalum capacitors and with 6x22 µF
ceramic capacitors at the input (full load).