Rainbow Electronics MAX3107 - Manual (Page 47)

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MAX3107
SPI/I
2
C UART with 128-Word FIFOs
and Internal Oscillator
Burst Read
With this operation the master sends an address and
receives multiple data bytes from the slave device
(Figure 21). The burst read procedure is as follows:
1) The master sends a START condition.
2) The master sends the 7-bit slave ID plus a write bit (low).
3) The addressed slave asserts an ACK on the data line.
4) The master sends the 8-bit register address.
5) The slave asserts an ACK on the data line only if the
address is valid (NACK if not).
6) The master sends a repeated START condition.
7) The master sends the 7-bit slave ID plus a read bit
(high). 8) The slave asserts an ACK on the data line.
9) The slave sends 8 bits of data.
10) The master asserts an ACK on the data line.
11) Repeat steps 9 and 10 N - 1 times.
12) The master generates a STOP condition.
Acknowledge
Data transfers are acknowledged with an acknowledge
bit (ACK) or a not-acknowledge bit (NACK). Both the
master and the MAX3107 generate ACK bits. To gener-
ate an ACK, pull SDA low before the rising edge of the
9th clock pulse and keep it low during the high period of
the 9th clock pulse (see Figure 22). To generate a NACK,
leave SDA high before the rising edge of the 9th clock
pulse and keep it high for the duration of the 9th clock
pulse. Monitoring for NACK bits allows for detection of
unsuccessful data transfers.
Applications Information
Startup and Initialization
The MAX3107 can be initialized following power-up or
a hardware or software reset as shown in Figure 23.
To verify that the MAX3107 is ready for operation after
a power-up or reset, check the IRQ output if interrupt
driven operation is employed.
In polled mode, repeatedly read a known register until
the expected contents are returned. Note that the con-
tents of the RevID change if new revisions of the product
are released. If reading RevID, it is recommended to only
check for the most significant 4 bits: Ah.
Low-Power Operation
Figure 21. Burst Read Sequence
Figure 22. Acknowledge
S
Sr
DEVICE SLAVE ADDRESS - W A
DEVICE SLAVE ADDRESS - R
BURST READ
A
REGISTER ADDRESS A
8 DATA BITS - 1 A
A 8 DATA BITS - 3 8 DATA BITS - 2 A
8 DATA BITS - N A
FROM MASTER TO STAVE FROM SLAVE TO MASTER
P
NOT ACKNOWLEDGE
ACKNOWLEDGE
1 2 8 9
SDA
SCL
S