Interrupt structure, Interrupt enabling, Interrupt clearing – Rainbow Electronics MAX3107 User Manual
Page 23: Detailed register descriptions, Interrupt enabling interrupt clearing, Figure 13. simplified interrupt structure, Rhr—receiver hold register, Max3107 spi/i, C uart with 128-word fifos and internal oscillator
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MAX3107
SPI/I
2
C UART with 128-Word FIFOs
and Internal Oscillator
Bits 7–0: RData[7:0]
The RHR is the bottom of the receive FIFO and is the register used for reading data out of the receive FIFO. It contains
the oldest (first received) character in the receive FIFO. RHR[0] is the LSB of the character received at the RX input. It
is the first data bit of the serial-data word received by the receiver.
Interrupt Structure
The structure of the interrupt is shown in Figure 13. There
are four interrupt source registers: ISR, LSR, STSInt, and
SpclCharInt. The interrupt sources are divided into top-
level and low-level interrupts. The top-level interrupts
typically occur more often and can be read out directly
through the ISR. The low-level interrupts typically occur
less often and their specific source can be read out
through the LSR, STSInt, or SpclChar registers. The three
LSBs of the ISR point to the low-level interrupt registers
that contain the source detail of the interrupt source.
Interrupt Enabling
Every interrupt bit of the four interrupt registers can be
enabled or masked through an associated interrupt
enable register bit. These are the IRQEn, LSRIntEn,
SpclChrIntEn and STSIntEn registers.
Interrupt Clearing
When an ISR interrupt is pending (i.e., any bit in ISR is
set) and the ISR is subsequently read, the ISR bits and
IRQ are cleared. Both the SpclCharInt and the STSInt
registers also are clear on read (COR). The LSR bits are
only cleared when the source of the interrupt is removed,
not when LSR is read.
Detailed Register Descriptions
The MAX3107 has a flat register structure, without shad-
ow registers, that makes programming and code simple
and efficient. All registers are 8 bits wide.
Figure 13. Simplified Interrupt Structure
RHR—Receiver Hold Register
7
6
5
4
3
2
1
0
ISR
8
[7]
IRQ
[0]
LOW-LEVEL INTERRUPTS
TOP-LEVEL INTERRUPTS
7
6
5
4
3
2
1
0
SpclChrIntEn
8
7
6
5
4
3
2
1
0
STSIntEn
8
7
6
5
4
3
2
1
0
LSRIntEn
8
ADDRESS:
0x00
MODE:
R
BIT
7
6
5
4
3
2
1
0
NAME
RData7
RData6
RData5
RData4
RData3
RData2
RData1
RData0
RESET
0
0
0
0
0
0
0
0