Max3107 spi/i, C uart with 128-word fifos and internal oscillator – Rainbow Electronics MAX3107 User Manual
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MAX3107
SPI/I
2
C UART with 128-Word FIFOs
and Internal Oscillator
Bits 7–0: TimOut[7:0]
The receive data timeout bits allow programming a time delay after the last (newest) character in the receive FIFO was
received until a receive data timeout LSR[0] interrupt is generated. The duration is measured in character intervals and
is dependent on the character length, parity, and STOP bit setting and is inversely proportional to the baud rate. If the
RxTimeOut value equals zero, a timeout interrupt is not generated.
The HDplxDelay register allows programming setup and hold times between RTS/CLKOUT and the TX output in auto-
matic transceiver direction control mode: MODE1[4] is 1. The Hold[3:0] time can also be used for echo suppression in
half-duplex communication. HDplxDelay also functions in the 2x and 4x rate modes.
Bits 7–4: Setup[7:4]
The Setupx bits define a setup time for RTS/CLKOUT to transition high before the transmitter starts transmission of its
first character in auto transceiver direction control mode: MODE1[4]. This allows the MAX3107 to account for skew dif-
ferences of the external transmitter’s enable delay and propagation delays. Setup[7:4] can also be used to fix a stable
state on the transmission line prior to start of transmission.
The unit of the HDplxDelay setup time delay is a 1-bit interval, making this delay baud-rate dependent. The maximum
delay is 15-bit intervals.
Bits 3–0: Hold[3:0]
The Hold[3:0] bits define a hold time for RTS/CLKOUT to be held stable (high) after the transmitter ends transmission
of its last character in auto transceiver direction control mode: MODE1[4]. RTS/CLKOUT turns low after the last STOP
bit was sent with a Hold[3:0] delay. This keeps the external transmitter enabled during the hold duration.
The second factor that the Hold[3:0] bits define, is a delay in echo suppression mode, MODE2[7]. See the Echo
Suppression section for more information.
The unit of the HDplxDelay hold time delay is a 1-bit interval, making the delay baud-rate dependent. The maximum
delay is 15-bit intervals.
RxTimeOut—Receiver Timeout Register
HDplxDelay Register
ADDRESS:
0x0C
MODE:
R/W
BIT
7
6
5
4
3
2
1
0
NAME
TimOut7
TimOut6
TimOut5
TimOut4
TimOutO3
TimOut2
TimOut1
TimOut0
RESET
0
0
0
0
0
0
0
0
ADDRESS:
0x0D
MODE:
R/W
BIT
7
6
5
4
3
2
1
0
NAME
Setup3
Setup2
Setup1
Setup0
Hold3
Hold2
Hold1
Hold0
RESET
0
0
0
0
0
0
0
0