Rainbow Electronics MAX3107 - Manual (Page 45)

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MAX3107
SPI/I
2
C UART with 128-Word FIFOs
and Internal Oscillator
Bit Transfer
One data bit is transferred during each SCL clock cycle.
The data on SDA must remain stable during the high
period of the SCL clock pulse. Changes in SDA while
SCL is high and stable are considered control signals
(see the START, STOP, and Repeated START Conditions
section). Both SDA and SCL remain high when the bus
is not active.
Single-Byte Write
With this operation the master sends an address and 1
or 2 data bytes to the slave device (Figure 18). The write
byte procedure is as follows:
1) The master sends a START condition.
2) The master sends the 7-bit slave ID plus a write bit (low).
3) The addressed slave asserts an ACK on the data line.
4) The master sends the 8-bit register address.
5) The active slave asserts an ACK on the data line only
if the address is valid (NACK if not).
6) The master sends the 8-bit data byte.
7) The slave asserts an ACK on the data line.
8) The master generates a STOP condition.
Figure 17. I 2 C START, STOP, and Repeated START Conditions
Table 5. I 2 C Address Map
Figure 18. Write Byte Sequence
SCL
SDA
S Sr P
S
P
DEVICE SLAVE ADDRESS - W A
8 DATA BITS
FROM MASTER TO STAVE
WRITE SINGLE BYTE
FROM SLAVE TO MASTER
A
REGISTER ADDRESS A
DIN/A1 CS/A0
READ/
WRITE
I 2 C ADDRESS
0 0
W 0x58
R 0x59
0 1
W 0x5A
R 0x5B
1 0
W 0x5C
R 0x5D
1 1
W 0x5E
R 0x5F