Rainbow Electronics MAX1717 User Manual
Page 27
MAX1717
Dynamically Adjustable, Synchronous
Step-Down Controller for Notebook CPUs
______________________________________________________________________________________
27
Power MOSFET Selection
Most of the following MOSFET guidelines focus on the
challenge of obtaining high load-current capability
(>12A) when using high-voltage (>20V) AC adapters.
Low-current applications usually require less attention.
For maximum efficiency, choose a high-side MOSFET
(Q1) that has conduction losses equal to the switching
losses at the optimum battery voltage (15V). Check to
ensure that the conduction losses at minimum input
voltage don’t exceed the package thermal limits or violate
the overall thermal budget. Check to ensure that con-
duction losses plus switching losses at the maximum
input voltage don’t exceed the package ratings or vio-
late the overall thermal budget.
Choose a low-side MOSFET (Q2) that has the lowest
possible R
DS(ON)
, comes in a moderate-sized package
(i.e., one or two SO-8s, DPAK or D
2
PAK), and is reason-
ably priced. Ensure that the MAX1717 DL gate driver
can drive Q2; in other words, check that the dv/dt
caused by Q1 turning on does not pull up the Q2 gate
due to drain-to-gate capacitance, causing cross-con-
duction problems. Switching losses aren’t an issue for
the low-side MOSFET since it’s a zero-voltage switched
device when used in the buck topology.
MOSFET Power Dissipation
Worst-case conduction losses occur at the duty factor
extremes. For the high-side MOSFET, the worst-case
power dissipation due to resistance occurs at minimum
battery voltage:
Generally, a small high-side MOSFET is desired to
reduce switching losses at high input voltages.
However, the R
DS(ON)
required to stay within package
power-dissipation limits often limits how small the
MOSFET can be. Again, the optimum occurs when the
switching losses equal the conduction (R
DS(ON)
) losses.
High-side switching losses don’t usually become an
issue until the input is greater than approximately 15V.
Switching losses in the high-side MOSFET can become
an insidious heat problem when maximum AC adapter
voltages are applied, due to the squared term in the
CV
2
f
SW
switching-loss equation. If the high-side
MOSFET you’ve chosen for adequate R
DS(ON)
at low
battery voltages becomes extraordinarily hot when sub-
jected to V
IN(MAX)
, reconsider your choice of MOSFET.
Calculating the power dissipation in Q1 due to switch-
ing losses is difficult since it must allow for difficult
quantifying factors that influence the turn-on and turn-
off times. These factors include the internal gate resis-
tance, gate charge, threshold voltage, source induc-
tance, and PC board layout characteristics. The following
switching-loss calculation provides only a very rough
estimate and is no substitute for breadboard evalua-
tion, preferably including verification using a thermo-
couple mounted on Q1:
where C
RSS
is the reverse transfer capacitance of Q1
and I
GATE
is the peak gate-drive source/sink current
(1A typ).
For the low-side MOSFET (Q2), the worst-case power
dissipation always occurs at maximum battery voltage:
The absolute worst case for MOSFET power dissipation
occurs under heavy overloads that are greater than
I
LOAD(MAX)
but are not quite high enough to exceed
the current limit and cause the fault latch to trip. To pro-
tect against this possibility, you can “overdesign” the
circuit to tolerate:
I
LOAD
= I
LIMIT(HIGH)
+ (LIR / 2) x I
LOAD(MAX)
where I
LIMIT(HIGH)
is the maximum valley current
allowed by the current-limit circuit, including threshold
tolerance and on-resistance variation. This means that
the MOSFETs must be very well heatsinked. If short-cir-
cuit protection without overload protection is enough, a
normal I
LOAD
value can be used for calculating compo-
nent stresses.
Choose a Schottky diode (D1) having a forward voltage
low enough to prevent the Q2 MOSFET body diode
from turning on during the dead time. As a general rule,
a diode having a DC current rating equal to 1/3 of the
load current is sufficient. This diode is optional and can
be removed if efficiency isn’t critical.
PD Q
V
V
I
R
OUT
IN MAX
LOAD
DS ON
(
)
(
)
(
)
2
1
2
=
×
−
PD Q Switching
C
V
f
I
I
RSS
IN MAX
SW
LOAD
GATE
(
)
(
)
1
2
=
Ч
Ч
Ч
PD Q
sistive
V
V
I
R
OUT
IN
LOAD
DS ON
(
Re
)
(
)
1
2
=
Ч
Ч