Rainbow Electronics MAX1717 User Manual
Page 26

MAX1717
Dynamically Adjustable, Synchronous
Step-Down Controller for Notebook CPUs
26
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Thus, the capacitor is usually selected by ESR and volt-
age rating rather than by capacitance value (this is true
of tantalums, OS-CONs, and other electrolytics).
When using low-capacity filter capacitors such as
ceramic or polymer types, capacitor size is usually deter-
mined by the capacity needed to prevent V
SAG
and
V
SOAR
from causing problems during load transients.
Generally, once enough capacitance is added to meet
the overshoot requirement, undershoot at the rising load
edge is no longer a problem (see the V
SAG
equation in
the Design Procedure section). The amount of overshoot
due to stored inductor energy can be calculated as:
where I
PEAK
is the peak inductor current.
Output Capacitor Stability
Considerations
Stability is determined by the value of the ESR zero rela-
tive to the switching frequency. The voltage-positioned
circuits in this data sheet have their ESR zero frequencies
lowered due to the external resistor in series with the
output capacitor ESR, guaranteeing stability. For voltage-
positioned circuits, the minimum ESR requirement of the
output capacitor is reduced by the voltage-positioning
resistor value.
For nonvoltage-positioned circuits, the following criteria
must be satisfied. The boundary of instability is given
by the following equation:
For a standard 300kHz application, the ESR zero fre-
quency must be well below 95kHz, preferably below
50kHz. Tantalum and OS-CON capacitors in widespread
use at the time of publication have typical ESR zero fre-
quencies of 15kHz. In the standard application used for
inductor selection, the ESR needed to support 50mV
P-P
ripple is 50mV/4.2A = 11.9m
Ω. Six 470µF/4V Kemet
T510 low-ESR tantalum capacitors in parallel provide
5m
Ω (max) ESR. Their typical combined ESR results in a
zero at 17kHz, well within the bounds of stability.
Do not put high-value ceramic capacitors directly
across the fast-feedback inputs (FB to GND) without
taking precautions to ensure stability. Ceramic capaci-
tors have a high ESR zero frequency and may cause
erratic, unstable operation. However, it’s easy to add
enough series resistance by placing the capacitors a
couple of inches downstream from the junction of the
inductor and FB pin, or use a voltage-positioned circuit
(see the Voltage Positioning and Effective Efficiency sec-
tion).
Unstable operation manifests itself in two related but
distinctly different ways: double-pulsing and fast-feed-
back loop instability.
Double-pulsing occurs due to noise on the output or
because the ESR is so low that there isn’t enough voltage
ramp in the output voltage signal. This “fools” the error
comparator into triggering a new cycle immediately
after the minimum off-time period has expired. Double-
pulsing is more annoying than harmful, resulting in noth-
ing worse than increased output ripple. However, it can
indicate the possible presence of loop instability, which
is caused by insufficient ESR.
Loop instability can result in oscillations at the output
after line or load perturbations that can cause the output
voltage to rise above or fall below the tolerance limit.
The easiest method for checking stability is to apply a
very fast zero-to-max load transient and carefully
observe the output voltage ripple envelope for over-
shoot and ringing. It can help to simultaneously monitor
the inductor current with an AC current probe. Don’t
allow more than one cycle of ringing after the initial
step-response under/overshoot.
Input Capacitor Selection
The input capacitor must meet the ripple current
requirement (I
RMS
) imposed by the switching currents
defined by the following equation:
For most applications, nontantalum chemistries (ceramic,
aluminum, or OS-CON) are preferred due to their resis-
tance to inrush surge currents typical of systems with a
mechanical switch or a connector in series with the bat-
tery. If the MAX1717 is operated as the second stage of
a two-stage power-conversion system, tantalum input
capacitors are acceptable. In either configuration,
choose an input capacitor that exhibits less than +10°C
temperature rise at the RMS input current for optimal
circuit longevity.
I
I
V
V
V
V
RMS
LOAD
OUT
IN
OUT
IN
=
(
)
−
/
:
f
f
where
f
R
C
ESR
SW
ESR
ESR
OUT
≤
=
Ч
Ч
Ч
π
π
1
2
V
L I
C
V
SOAR
PEAK
OUT
≈
Ч
Ч
Ч
2
2