Rainbow Electronics DS2432 - Manual (Page 13)

PRELIMINARY DS2432
13 of 30
Memory and SHA Functions Flow Chart (continued) Figure 7
A5h
Read Auth.
Page ?
Bus Master TX
TA1 (T7:T0), TA2 (T15:T8)
Y
N
Y
N
Address
< 80h ?
N
Bus Master
RX “1”s
Master
TX Reset ?
Y
DS2432 sets Memory
Address = (T15:T0)
Master
TX Reset ?
Y
N
Bus Master RX CRC16
of Command, Address,
Data, and FFh Byte
DS2432
Increments
Address
Counter
Master
TX Reset ?
Master RX Data Byte
From Memory Address
N
Y
End
Of Page ?
N
Y
Master RX
one byte FFh
Master
TX Reset ?
Master
TX Reset ?
Y
N
DS2432 TX “1”
DS2432 TX “0”
N
Y
SHA Engine Computes
Message Authentication
Code of Secret, Data of
Selected Page, Device
Registration Number and
3-Byte Challenge
Bus Master RX 160-Bit
Message Auth. Code
Bus Master RX CRC16 of
Message Auth. Code
*
1-Wire idle high for power
Note: Three bytes of the
scratchpad contents are taken
as a challenge to the DS2432.
The master may specify the
challenge or accept the current
scratchpad contents instead.
*
From Figure 7
5
th
Part
To Figure 7
5
th
Part
To Figure 7
7
th
Part
From Figure 7
7
th
Part