Block diagram, Memory array – Rainbow Electronics AT25DF081 User Manual
Page 4
4
3674E–DFLASH–8/08
AT25DF081
3.
Block Diagram
4.
Memory Array
To provide the greatest flexibility, the memory array of the AT25DF081 can be erased in four lev-
els of granularity including a full chip erase. In addition, the array has been divided into physical
sectors of uniform size, of which each sector can be individually protected from program and
erase operations. The size of the physical sectors is optimized for both code and data storage
applications, allowing both code and data segments to reside in their own isolated
regions.
illustrates the breakdown of each erase level as well as the break-
down of each physical sector.
Figure 2-1.
8-SOIC Top View
Figure 2-2.
8-UDFN Top View
Figure 2-3.
11-dBGA (Top View
Through Back of Die)
1
2
3
4
8
7
6
5
CS
SO
WP
GND
VCC
HOLD
SCK
SI
CS
SO
WP
GND
VCC
HOLD
SCK
SI
8
7
6
5
1
2
3
4
A
B
C
D
E
F
1
2
3
4
NC
VCC
HOLD
SCK
SI
CS
SO
WP
GND
NC
NC
FLASH
MEMORY
ARRAY
Y-GATING
CS
SCK
SO
SI
Y-DECODER
ADDRESS LA
TCH
X-DECODER
I/O BUFFERS
AND LATCHES
CONTROL AND
PROTECTION LOGIC
SRAM
DATA BUFFER
WP
INTERFACE
CONTROL
AND
LOGIC
HOLD